mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #456 from naichewa/main
fifo fixes and edge case testing
This commit is contained in:
David Harris
GitHub
commit
b1994f12fa
@ -26,15 +26,16 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Current limitations: Flash read sequencer mode not implemented, dual and quad modes untestable with current test plan.
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// Hardware interlock change to busy signal
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// write tests for fifo full and empty watermark edge cases
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// test case for two's complement rollover on fifo watermark calculation + watermark calc redesign
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// rempty triggers when fifo full, txmark = 7 doesnt work
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// HoldModeDeassert make sure still works
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// Comment on FIFOs: watermark calculations
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// Comment all interface and internal signals on the lines they are declared
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// Get tabs correct so things line up
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// Relook at frame compare/ Delay count logic w/o multibit
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// look at ReadIncrement/WriteIncrement delay necessity
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// test case for two's complement rollover on fifo watermark calculation + watermark calc redesign
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/* high level explanation of architecture
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SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers.
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The FIFOs are connected to WALLY by an apb bus control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
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@ -153,8 +154,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// APB access
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assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign Memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign PREADY = 1'b1; // tie high if hardware interlock solution doesn't involve bus
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//assign PREADY = TransmitInactive; // tie PREADY to transmission for hardware interlock
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assign PREADY = TransmitInactive; // tie PREADY to transmission for hardware interlock
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// account for subword read/write circuitry
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// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
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@ -249,7 +249,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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ReceiveShiftFSM ReceiveShiftFSM_1 (PCLK, PRESETn, SCLKenable, ReceivePenultimateFrameBoolean, SampleEdge, SckMode[0], ReceiveShiftFull);
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//calculate tx/rx fifo write and recieve increment signals
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assign TransmitFIFOWriteIncrement = (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull);
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assign TransmitFIFOWriteIncrement = (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive);
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) TransmitFIFOWriteIncrementDelay <= 0;
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@ -358,7 +358,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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assign PWChipSelect = PWDATA[3:0];
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always_ff @(posedge PCLK, negedge PRESETn)
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if (~PRESETn) HoldModeDeassert <= 0;
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else if (~Inactive & ((ChipSelectMode[1:0] == 2'b10) & (Entry == (8'h18 | 8'h10) | ((Entry == 8'h14) & (PWChipSelect[ChipSelectID] != ChipSelectDef[ChipSelectID])))) & Memwrite) HoldModeDeassert <= 1;
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else if (~Inactive & Memwrite & ((ChipSelectMode[1:0] == 2'b10) & (Entry == (8'h18 | 8'h10) | ((Entry == 8'h14) & (PWChipSelect[ChipSelectID] != ChipSelectDef[ChipSelectID]))))) HoldModeDeassert <= 1;
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// Signal tracks which edge of sck to shift data
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always_comb
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@ -455,10 +455,9 @@ module SynchFIFO #(parameter M =3 , N= 8)(
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assign raddr = rptr[M-1:0];
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assign rptrnext = rptr + {3'b0, (rinc & ~rempty)};
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assign rempty_val = (wptr == rptrnext);
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assign rwatermark = ((raddr - waddr) < rwatermarklevel);
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assign rwatermark = ((waddr - raddr) < rwatermarklevel) & ~wfull;
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assign waddr = wptr[M-1:0];
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assign wwatermark = ((waddr - raddr) > wwatermarklevel);
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assign wwatermark = ((waddr - raddr) > wwatermarklevel) | wfull;
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assign wptrnext = wptr + {3'b0, (winc & ~wfull)};
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assign wfull_val = ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
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endmodule
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@ -13,7 +13,7 @@
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00000001 # delay 1
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00080000 # fmt
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00000000 # tx_data
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00000000 # tx_mark
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@ -23,6 +23,62 @@
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00000000 # ie reset
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00000000 # ip reset
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00000000 # fifo watermark and edge case tests
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00000001
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00000003
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00000003
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00000074
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00000063
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00000052
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00000041
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000000A1
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00000003
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000000B2
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00000001
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000000C3
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000000D4
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00000003
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000000A4
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00000001
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000000B4
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000000A5
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000000B5
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000000C5
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000000D5
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000000A7
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000000B7
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000000C7
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00000002
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000000D7
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00000000
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00000011 #basic read write
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@ -116,6 +172,8 @@
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000000AB
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000000CE hold mode deassert
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000000F0 #fmt register
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00000000
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@ -146,12 +204,52 @@
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0000001F
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00000062 # hardware interlock
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00000026
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000000D2
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0000002D
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00000048
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00000037
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00000026
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00000015
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00000084
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00000073
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00000062
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00000051
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00000046
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00000035
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00000024
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00000013
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00000064
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00000053
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00000042
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00000031
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00000001 #watermark interrupts
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00000000 #read mip
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00000000 #read tx ip
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00000022 #clear 1 frame from rx fifo
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00000000 # read recieve ip
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@ -170,24 +268,21 @@
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00000001 #read tx ip
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00000800 #read mip 11
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00000800 #read mip
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00000000 #read tx wm 10
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00000022 #clear frame
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00000000 #read mip 91 9
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00000000 #read rx ip
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00000022 #clear frame 8
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00000000 #read mip 94
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00000000 #read rx ip 7
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00000002 #read rx ip
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00000000 #read mip 94 6
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00000800 #read mip
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00000002 #read rx ip 5
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00000033 #clear frame
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00000800 #read mip 4
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00000000 #read rx wm
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00000033 #clear frame 3
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00000000 #read mip 99
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00000000 #read rx wm 2
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00000000 #read mip 99 1
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@ -115,6 +115,68 @@ test_cases:
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.4byte ie, 0x00000000, read32_test # ie reset to 0x0
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.4byte ip, 0x00000000, read32_test # ip reset to 0x0
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#test watermark interrupts at beginning where fifo read/write pointers are known b/c reset
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# txwmp raised when # of entries in txfifo < txmark, rxwm raised when # of entries in rxfifo > rxmark
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.4byte ip, 0x00000000, read32_test # txfifo entries not < 0, rxfifo entries not > 0;
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.4byte tx_mark, 0x00000004, write32_test # set tx_mark to 4
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.4byte rx_mark, 0x00000003, write32_test # set rx_mark to 3
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.4byte ip, 0x00000001, read32_test # tx entries < 4, rx entries ! > 3
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.4byte tx_data, 0x41526374, spi_burst_send
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.4byte 0x0, 0x00000003, spi_data_wait
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.4byte ip, 0x00000003, read32_test # tx entries < 4, rx entries > 3, visual inspection should see tx TransmitFIFOReadIncrement
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# txfifo wptr now at 0011, rxfifo wptr at 0000
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.4byte rx_mark, 0x00000007, write32_test # set rx_mark to 7
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.4byte tx_data, 0xD4C3B2A1, spi_burst_send
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.4byte 0x0, 0x00000007, spi_data_wait # rxfifo full, txfifo wptr at 1000, rxfifo wptr at 0000
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.4byte ip, 0x00000003, read32_test
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.4byte rx_data, 0x00000074, read32_test
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.4byte rx_data, 0x00000063, read32_test # clear 2 entries, txfifo wptr at 1000, rxfifo wptr at 0010
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.4byte tx_data, 0x000000A4, write32_test
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.4byte tx_data, 0x000000B4, write32_test # tx 1010, rx 0010
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.4byte 0x0, 0x00000007, spi_data_wait # 8 tx 1010, rx 0010
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.4byte rx_mark, 0x00000004, write32_test
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.4byte rx_data, 0x00000052, read32_test # 7 rx 0011
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.4byte rx_data, 0x00000041, read32_test # 6 rx 0100
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.4byte rx_data, 0x000000A1, read32_test # 5 rx 0101
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.4byte ip, 0x00000003, read32_test # 5 things in rx fifo
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.4byte rx_data, 0x000000B2, read32_test # 4 tx 1010, rx 0110
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.4byte ip, 0x00000001, read32_test # 4 entries in rxfifo, not strictly greater than 4
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.4byte rx_mark, 0x00000007, write32_test
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.4byte tx_data, 0xD5C5B5A5, spi_burst_send # 8 tx1110, rx 0110
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.4byte 0x0, 0x00000007, spi_data_wait
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.4byte rx_mark, 0x00000005, write32_test
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.4byte rx_data, 0x000000C3, read32_test # tx 1110, rx 0111
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.4byte rx_data, 0x000000D4, read32_test # tx 1110, rx 1000
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.4byte ip, 0x00000003, read32_test # 6 entries
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.4byte rx_data, 0x000000A4, read32_test # tx 1110, rx 1001
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.4byte ip, 0x00000001, read32_test # 5 entries
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.4byte rx_data, 0x000000B4, read32_test # tx 1110, rx 1010
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.4byte rx_data, 0x000000A5, read32_test # tx 1110, rx 1011
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.4byte rx_mark, 0x00000006, write32_test
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.4byte tx_data, 0xD7C7B7A7, spi_burst_send
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.4byte 0x0, 0x00000006, spi_data_wait # tx 0010, rx 1011
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.4byte tx_mark, 0x00000000, write32_test
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.4byte rx_mark, 0x00000000, write32_test
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.4byte rx_data, 0x000000B5, read32_test # tx 0010, rx 1100
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.4byte rx_data, 0x000000C5, read32_test # tx 0010, rx 1101
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.4byte rx_data, 0x000000D5, read32_test # tx 0010, rx 1110
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.4byte rx_data, 0x000000A7, read32_test # tx 0010, rx 1111
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.4byte rx_data, 0x000000B7, read32_test # tx 0010, rx 0000
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.4byte rx_data, 0x000000C7, read32_test # tx 0010, rx 0001
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.4byte ip, 0x00000002, read32_test
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.4byte rx_data, 0x000000D7, read32_test # tx 0010, rx 1010
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.4byte ip, 0x00000000, read32_test
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.4byte tx_mark, 0x00000000, write32_test
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.4byte rx_mark, 0x00000000, write32_test # reset watermark registers
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# =========== Basic read-write ===========
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.4byte tx_data, 0x000000011, write32_test # place 8'h11 into tx_data
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@ -226,7 +288,7 @@ test_cases:
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# Test arbitrary sck-cs delay (sck phase 1)
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.4byte delay0, 0x00000501, write32_test # set cs-sck delay to A5 cycles
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.4byte delay0, 0x00050001, write32_test # set cs-sck delay to A5 cycles
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.4byte tx_data, 0x00000011, write32_test # place 8'h11 into tx_data
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.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
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.4byte rx_data, 0x00000011, read32_test # read rx_data
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@ -246,6 +308,7 @@ test_cases:
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.4byte delay0, 0x00010001, write32_test # reset delay0 register
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.4byte delay1, 0x00000005, write32_test # set inter_cs delay to 5
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x44332211, spi_burst_send
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.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
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.4byte rx_data, 0x00000011, read32_test
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@ -256,6 +319,7 @@ test_cases:
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#test long inter_cs delay
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.4byte delay1, 0x000000A5, write32_test
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.4byte rx_mark, 0x0000000, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x0000007B, write32_test
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.4byte 0x0, 0x00000000, spi_data_wait
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.4byte rx_data, 0x0000007B, read32_test
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@ -264,6 +328,7 @@ test_cases:
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# Test inter_cs delay set to 0
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.4byte delay1, 0x00000000, write32_test # set inter_cs delay to 5
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x54433221, spi_burst_send
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.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
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.4byte rx_data, 0x00000021, read32_test
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@ -306,6 +371,7 @@ test_cases:
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# test long inter_xfr delay
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.4byte delay1, 0x00A50001, write32_test
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.4byte rx_mark, 0x0000000, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x00000048, write32_test
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.4byte 0x0, 0x00000000, spi_data_wait
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.4byte rx_data, 0x00000048, read32_test
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@ -314,6 +380,7 @@ test_cases:
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.4byte delay1, 0x00000001, write32_test # set inter_xfr delay to 0
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.4byte delay0, 0x00010005, write32_test # set cs-sck delay to 5 (should have no effect because cs is never inactive)
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0xAABBCCDD, spi_burst_send
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.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
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.4byte rx_data, 0x000000DD, read32_test # read rx_data
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@ -323,7 +390,7 @@ test_cases:
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# Test sck-cs delay cs_mode = HOLD
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.4byte delay0, 0x00050001, write32_test # set sck-cs delay to 5 (should have no effect because cs is never inactive)
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.4byte delay0, 0x00000501, write32_test # set sck-cs delay to 5 (should have no effect because cs is never inactive)
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.4byte tx_data, 0xABBCCDDE, spi_burst_send # place 8'h11 into tx_data
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.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
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.4byte rx_data, 0x000000DE, read32_test # read rx_data
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@ -331,6 +398,18 @@ test_cases:
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.4byte rx_data, 0x000000BC, read32_test
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.4byte rx_data, 0x000000AB, read32_test
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# Test hold mode deassert conditions
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.4byte delay1, 0x00000001, write32_test # reset delay1 register
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.4byte delay0, 0x00010001, write32_test # reset delay0 register
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.4byte cs_mode, 0x00000002, write32_test # set cs_mode to hold
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.4byte tx_data, 0x000000CE, write32_test # place data into tx_data
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.4byte cs_id, 0x00000001, write32_test #change selected cs pin. should deassert cs[0] in hold mode
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.4byte cs_def, 0x00001101, write32_test # change selected cs pins def value. should deassert cs[1]
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.4byte cs_def, 0x00001111, write32_test # reset cs_def
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.4byte cs_mode, 0x00000000, write32_test # change cs_mode to auto, should deassert cs[1], have now gone through all deassertion conditions
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.4byte rx_data, 0x000000CE, read32_test # clear rx_fifo
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# =========== Test frame format (fmt) register ===========
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# Test frame length of 4
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@ -340,6 +419,7 @@ test_cases:
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.4byte sck_mode, 0x00000000, write32_test #reset sckmode register
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.4byte cs_mode, 0x00000000, write32_test # set cs_mode to AUTO
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.4byte fmt, 0x00040000, write32_test # set frame length to 4
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.4byte rx_mark, 0x0000000, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x000000F0, write32_test # place 8'h11 into tx_data
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.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
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.4byte rx_data, 0x000000F0, read32_test # read rx_data
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@ -353,6 +433,7 @@ test_cases:
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# test frame length 1 burst
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.4byte fmt, 0x00010000, write32_test
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x80008000, spi_burst_send
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.4byte 0x0, 0x00000003, spi_data_wait
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.4byte rx_data, 0x00000000, read32_test
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@ -364,12 +445,14 @@ test_cases:
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# Test big endian with frame length = 5
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.4byte fmt, 0x00050000, write32_test # set frame length to 5, big endian
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.4byte rx_mark, 0x0000000, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x000000A8, write32_test # place 8'h11 into tx_data
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.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
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.4byte rx_data, 0x000000A8, read32_test # read rx_data
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# Test big endian burst with frame length = 5
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x03774FFF, spi_burst_send
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.4byte 0x0, 0x00000003, spi_data_wait
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.4byte rx_data, 0x000000F8, read32_test
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@ -383,12 +466,14 @@ test_cases:
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# Test little endian with frame length = 5
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|
||||
.4byte fmt, 0x00050004, write32_test # set frame length to 5, little-endian
|
||||
.4byte rx_mark, 0x0000000, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte tx_data, 0x000000A8, write32_test # place 8'h11 into tx_data
|
||||
.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
.4byte rx_data, 0x00000008, read32_test # read rx_data -> 08
|
||||
|
||||
#test little endian burst with frame length = 5
|
||||
|
||||
.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte tx_data, 0xFF4F7703, spi_burst_send
|
||||
.4byte 0x0, 0x00000003, spi_data_wait
|
||||
.4byte rx_data, 0x00000003, read32_test #03
|
||||
@ -446,20 +531,116 @@ test_cases:
|
||||
#.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
#.4byte rx_data, 0x000000F0, read32_test # read rx_data
|
||||
|
||||
#=========== Test Hardware Interlock ================
|
||||
|
||||
# interlock in base case
|
||||
|
||||
.4byte fmt, 0x00080000, write32_test # reset fmt register
|
||||
.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte tx_data, 0x00000062, write32_test # initiate transmission
|
||||
.4byte sck_mode, 0x00000002, write32_test # flip polarity during transmission
|
||||
.4byte tx_data, 0x00000026, write32_test # transmit second frame w/ control register updated
|
||||
.4byte 0x0, 0x00000001, spi_data_wait
|
||||
.4byte rx_data, 0x00000062, read32_test
|
||||
.4byte rx_data, 0x00000026, read32_test # clear rx fifo
|
||||
.4byte sck_mode, 0x00000000, write32_test # reset polarity
|
||||
|
||||
# interlock in case where cs_mode is auto, but there is minimal intercs delay
|
||||
|
||||
.4byte delay0, 0x00000001, write32_test # set sck-cs delay to 0, with sck.pha 0 there is 0 delay
|
||||
.4byte tx_data, 0x000000D2, write32_test # initiate transmission
|
||||
.4byte sck_mode, 0x00000002, write32_test # flip sck polarity
|
||||
.4byte tx_data, 0x0000002D, write32_test # transmit second frame
|
||||
.4byte 0x0, 0x00000001, spi_data_wait
|
||||
.4byte rx_data, 0x000000D2, read32_test
|
||||
.4byte rx_data, 0x0000002D, read32_test # clear rx fifo
|
||||
.4byte sck_mode, 0x00000000, write32_test # reset polarity
|
||||
|
||||
# interlock in case where cs_mode = hold, 0 intercs delay
|
||||
.4byte delay0, 0x00010001, write32_test # reset delay0
|
||||
.4byte sck_mode, 0x00000000, write32_test # reset polarity
|
||||
.4byte cs_mode, 0x00000002, write32_test # set cs_mode to hold
|
||||
.4byte tx_data, 0x15263748, spi_burst_send # place 4 frames into tx fifo
|
||||
.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
|
||||
.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
|
||||
.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte sck_mode, 0x00000000, write32_test # flip polarity again
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
|
||||
.4byte rx_data, 0x00000048, read32_test
|
||||
.4byte rx_data, 0x00000037, read32_test
|
||||
.4byte rx_data, 0x00000026, read32_test
|
||||
.4byte rx_data, 0x00000015, read32_test #clear rx fifo
|
||||
|
||||
# interlock in case where cs_mode = hold, intercs delay
|
||||
|
||||
.4byte sck_mode, 0x00000000, write32_test # reset polarity
|
||||
.4byte delay1, 0x00010001, write32_test # set intercs delay to 1
|
||||
.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte tx_data, 0x51627384, spi_burst_send # place 4 frames into tx fifo
|
||||
.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
|
||||
.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
|
||||
.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte sck_mode, 0x00000000, write32_test # flip polarity again
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
|
||||
.4byte rx_data, 0x00000084, read32_test
|
||||
.4byte rx_data, 0x00000073, read32_test
|
||||
.4byte rx_data, 0x00000062, read32_test
|
||||
.4byte rx_data, 0x00000051, read32_test #clear rx fifo
|
||||
|
||||
# repeat previous set of tests with cs_mode = off
|
||||
|
||||
.4byte cs_mode, 0x00000003, write32_test # set cs_mode to hold
|
||||
.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte tx_data, 0x13243546, spi_burst_send # place 4 frames into tx fifo
|
||||
.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
|
||||
.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
|
||||
.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte sck_mode, 0x00000000, write32_test # flip polarity again
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
|
||||
.4byte rx_data, 0x00000046, read32_test
|
||||
.4byte rx_data, 0x00000035, read32_test
|
||||
.4byte rx_data, 0x00000024, read32_test
|
||||
.4byte rx_data, 0x00000013, read32_test #clear rx fifo
|
||||
|
||||
# interlock in case where cs_mode = hold, intercs delay
|
||||
|
||||
.4byte sck_mode, 0x00000000, write32_test # reset polarity
|
||||
.4byte delay1, 0x00000000, write32_test # set intercs delay to 0
|
||||
.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte tx_data, 0x31425364, spi_burst_send # place 4 frames into tx fifo
|
||||
.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
|
||||
.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
|
||||
.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
|
||||
.4byte sck_mode, 0x00000000, write32_test # flip polarity again
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
|
||||
.4byte rx_data, 0x00000064, read32_test
|
||||
.4byte rx_data, 0x00000053, read32_test
|
||||
.4byte rx_data, 0x00000042, read32_test
|
||||
.4byte rx_data, 0x00000031, read32_test #clear rx fifo
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
# =========== Test watermark interrupts ===========
|
||||
|
||||
# Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables
|
||||
# rx fifo > rx mark
|
||||
|
||||
SETUP_PLIC
|
||||
|
||||
.4byte fmt, 0x00080000, write32_test # reset fmt register
|
||||
.4byte tx_mark, 0x00000004, write32_test # set transmit watermark to 4
|
||||
.4byte delay1, 0x0000001, write32_test # reset delay1 register
|
||||
.4byte cs_mode, 0x00000000, write32_test # reset cs_mode
|
||||
.4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off)
|
||||
#.4byte ie, 0x00000000, write32_test # enable transmit interrupt
|
||||
.4byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
.4byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.4byte ip, 0x00000000, read32_test # tx watermark interupt should be off
|
||||
.4byte ip, 0x00000000, read32_test # tx watermark interupt should be off 125
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
@ -478,23 +659,18 @@ SETUP_PLIC
|
||||
.4byte rx_data, 0x00000055, read32_test # clear rx fifo
|
||||
|
||||
|
||||
.4byte tx_mark, 0x00000004, write32_test # set transmit watermark to 4
|
||||
.4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 0
|
||||
.4byte ie, 0x00000001, write32_test # enable transmit interrupt
|
||||
.4byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.4byte 0x0, 0x00000800, readmip_test
|
||||
.4byte ie, 0x00000000, write32_test #turn off tx mark
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts
|
||||
.4byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.4byte ie, 0x00000001, write32_test #turn tx mark back on
|
||||
.4byte tx_mark, 0x00000001, write32_test
|
||||
.4byte ip, 0x00000000, read32_test # tx watermark interupt should be off
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
.4byte ie, 0x00000000, write32_test # disable tx intr
|
||||
.4byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
|
||||
.4byte tx_mark, 0x00000000, write32_test
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts
|
||||
.4byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO
|
||||
.4byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3
|
||||
.4byte ie, 0x0000002, write32_test # enable receive interrupts
|
||||
@ -508,4 +684,6 @@ SETUP_PLIC
|
||||
.4byte ip, 0x00000000, read32_test # receive interrupt should be low
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
|
||||
|
||||
|
||||
.4byte 0x0, 0x0, terminate_test
|
||||
@ -24,6 +24,62 @@
|
||||
00000000
|
||||
00000000 # ip reset
|
||||
00000000
|
||||
00000000 # fifo watermark and edge case tests
|
||||
00000000
|
||||
00000001
|
||||
00000000
|
||||
00000003
|
||||
00000000
|
||||
00000003
|
||||
00000000
|
||||
00000074
|
||||
00000000
|
||||
00000063
|
||||
00000000
|
||||
00000052
|
||||
00000000
|
||||
00000041
|
||||
00000000
|
||||
000000A1
|
||||
00000000
|
||||
00000003
|
||||
00000000
|
||||
000000B2
|
||||
00000000
|
||||
00000001
|
||||
00000000
|
||||
000000C3
|
||||
00000000
|
||||
000000D4
|
||||
00000000
|
||||
00000003
|
||||
00000000
|
||||
000000A4
|
||||
00000000
|
||||
00000001
|
||||
00000000
|
||||
000000B4
|
||||
00000000
|
||||
000000A5
|
||||
00000000
|
||||
000000B5
|
||||
00000000
|
||||
000000C5
|
||||
00000000
|
||||
000000D5
|
||||
00000000
|
||||
000000A7
|
||||
00000000
|
||||
000000B7
|
||||
00000000
|
||||
000000C7
|
||||
00000000
|
||||
00000002
|
||||
00000000
|
||||
000000D7
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000011 #basic read write
|
||||
00000000
|
||||
000000FF
|
||||
@ -116,25 +172,8 @@
|
||||
00000000
|
||||
000000AB
|
||||
00000000
|
||||
#000000CE hold mode deassert
|
||||
#00000000
|
||||
#00000002 #fifo edge case
|
||||
#00000000
|
||||
#000000D1
|
||||
#00000000
|
||||
#000000C1
|
||||
#00000000
|
||||
#000000B1
|
||||
#00000000
|
||||
#000000A1
|
||||
#0000001B
|
||||
#00000000
|
||||
#0000001A
|
||||
#00000000
|
||||
#000000F1
|
||||
#00000000
|
||||
#000000E1
|
||||
#00000000
|
||||
000000CE hold mode deassert
|
||||
00000000
|
||||
000000F0 #fmt register
|
||||
00000000
|
||||
00000000
|
||||
@ -231,10 +270,6 @@
|
||||
00000000
|
||||
00000800 #read mip
|
||||
00000000
|
||||
00000000 #read tx wm
|
||||
00000000
|
||||
00000000 #read mip 91
|
||||
00000000
|
||||
00000022 #clear frame
|
||||
00000000
|
||||
00000000 #read rx ip
|
||||
|
||||
@ -85,6 +85,70 @@ test_cases:
|
||||
.8byte ie, 0x00000000, read32_test # ie reset to 0x0
|
||||
.8byte ip, 0x00000000, read32_test # ip reset to 0x0
|
||||
|
||||
# =========== watermark interrupts ===============
|
||||
|
||||
#test watermark interrupts at beginning where fifo read/write pointers are known b/c reset
|
||||
# txwmp raised when # of entries in txfifo < txmark, rxwm raised when # of entries in rxfifo > rxmark
|
||||
|
||||
.8byte ip, 0x00000000, read32_test # txfifo entries not < 0, rxfifo entries not > 0;
|
||||
.8byte tx_mark, 0x00000004, write32_test # set tx_mark to 4
|
||||
.8byte rx_mark, 0x00000003, write32_test # set rx_mark to 3
|
||||
.8byte ip, 0x00000001, read32_test # tx entries < 4, rx entries ! > 3
|
||||
.8byte tx_data, 0x41526374, spi_burst_send
|
||||
.8byte 0x0, 0x00000003, spi_data_wait
|
||||
.8byte ip, 0x00000003, read32_test # tx entries < 4, rx entries > 3, visual inspection should see tx TransmitFIFOReadIncrement
|
||||
|
||||
# txfifo wptr now at 0011, rxfifo wptr at 0000
|
||||
|
||||
.8byte rx_mark, 0x00000007, write32_test # set rx_mark to 7
|
||||
.8byte tx_data, 0xD4C3B2A1, spi_burst_send
|
||||
.8byte 0x0, 0x00000007, spi_data_wait # rxfifo full, txfifo wptr at 1000, rxfifo wptr at 0000
|
||||
.8byte ip, 0x00000003, read32_test
|
||||
.8byte rx_data, 0x00000074, read32_test
|
||||
.8byte rx_data, 0x00000063, read32_test # clear 2 entries, txfifo wptr at 1000, rxfifo wptr at 0010
|
||||
|
||||
|
||||
.8byte tx_data, 0x000000A4, write32_test
|
||||
.8byte tx_data, 0x000000B4, write32_test # tx 1010, rx 0010
|
||||
.8byte 0x0, 0x00000007, spi_data_wait # 8 tx 1010, rx 0010
|
||||
.8byte rx_mark, 0x00000004, write32_test
|
||||
.8byte rx_data, 0x00000052, read32_test # 7 rx 0011
|
||||
.8byte rx_data, 0x00000041, read32_test # 6 rx 0100
|
||||
.8byte rx_data, 0x000000A1, read32_test # 5 rx 0101
|
||||
.8byte ip, 0x00000003, read32_test # 5 things in rx fifo
|
||||
.8byte rx_data, 0x000000B2, read32_test # 4 tx 1010, rx 0110
|
||||
.8byte ip, 0x00000001, read32_test # 4 entries in rxfifo, not strictly greater than 4
|
||||
|
||||
.8byte rx_mark, 0x00000007, write32_test
|
||||
.8byte tx_data, 0xD5C5B5A5, spi_burst_send # 8 tx1110, rx 0110
|
||||
.8byte 0x0, 0x00000007, spi_data_wait
|
||||
|
||||
.8byte rx_mark, 0x00000005, write32_test
|
||||
.8byte rx_data, 0x000000C3, read32_test # tx 1110, rx 0111
|
||||
.8byte rx_data, 0x000000D4, read32_test # tx 1110, rx 1000
|
||||
.8byte ip, 0x00000003, read32_test # 6 entries
|
||||
.8byte rx_data, 0x000000A4, read32_test # tx 1110, rx 1001
|
||||
.8byte ip, 0x00000001, read32_test # 5 entries
|
||||
.8byte rx_data, 0x000000B4, read32_test # tx 1110, rx 1010
|
||||
.8byte rx_data, 0x000000A5, read32_test # tx 1110, rx 1011
|
||||
|
||||
.8byte rx_mark, 0x00000006, write32_test
|
||||
.8byte tx_data, 0xD7C7B7A7, spi_burst_send
|
||||
.8byte 0x0, 0x00000006, spi_data_wait # tx 0010, rx 1011
|
||||
.8byte tx_mark, 0x00000000, write32_test
|
||||
.8byte rx_mark, 0x00000000, write32_test
|
||||
.8byte rx_data, 0x000000B5, read32_test # tx 0010, rx 1100
|
||||
.8byte rx_data, 0x000000C5, read32_test # tx 0010, rx 1101
|
||||
.8byte rx_data, 0x000000D5, read32_test # tx 0010, rx 1110
|
||||
.8byte rx_data, 0x000000A7, read32_test # tx 0010, rx 1111
|
||||
.8byte rx_data, 0x000000B7, read32_test # tx 0010, rx 0000
|
||||
.8byte rx_data, 0x000000C7, read32_test # tx 0010, rx 0001
|
||||
.8byte ip, 0x00000002, read32_test
|
||||
.8byte rx_data, 0x000000D7, read32_test # tx 0010, rx 1010
|
||||
.8byte ip, 0x00000000, read32_test
|
||||
.8byte tx_mark, 0x00000000, write32_test
|
||||
.8byte rx_mark, 0x00000000, write32_test # reset watermark registers
|
||||
|
||||
# =========== Basic read-write ===========
|
||||
|
||||
.8byte tx_data, 0x000000011, write32_test # place 8'h11 into tx_data
|
||||
@ -308,32 +372,15 @@ test_cases:
|
||||
|
||||
# Test hold mode deassert conditions
|
||||
|
||||
#.8byte delay1, 0x00000001, write32_test # reset delay1 register
|
||||
#.8byte delay0, 0x00010001, write32_test # reset delay0 register
|
||||
#.8byte cs_mode, 0x00000002, write32_test # set cs_mode to hold
|
||||
#.8byte tx_data, 0x000000CE, write32_test # place data into tx_data
|
||||
#.8byte cs_id, 0x00000001, write32_test #change selected cs pin. should deassert cs[0] in hold mode
|
||||
#.8byte cs_def, 0x00001101, write32_test # change selected cs pins def value. should deassert cs[1]
|
||||
#.8byte cs_def, 0x00001111, write32_test # reset cs_def
|
||||
#.8byte cs_mode, 0x00000000, write32_test # change cs_mode to auto, should deassert cs[1], have now gone through all deassertion conditions
|
||||
#.8byte rx_data, 0x000000CE, read32_test # clear rx_fifo
|
||||
|
||||
# Test transmit and receive fifo full edge cases
|
||||
#.8byte rx_mark, 0x00000007, write32_test #set rx watermark to 7 (only high when full)
|
||||
#.8byte tx_data, 0xA1B1C1D1, spi_burst_send #fill rx fifo
|
||||
#.8byte tx_data, 0xE1F11A1B, spi_burst_send
|
||||
#.8byte 0x0, 0x00000007, spi_data_wait #wait for rx fifo to fill
|
||||
#.8byte ip, 0x00000002, read32_test #rxmark ip should be high
|
||||
#.8byte rx_data, 0x000000D1, read32_test #clear rx fifo
|
||||
#.8byte rx_data, 0x000000C1, read32_test
|
||||
#.8byte rx_data, 0x000000B1, read32_test
|
||||
#.8byte rx_data, 0x000000A1, read32_test
|
||||
#.8byte rx_data, 0x0000001B, read32_test
|
||||
#.8byte rx_data, 0x0000001A, read32_test
|
||||
#.8byte rx_data, 0x000000F1, read32_test
|
||||
#.8byte rx_data, 0x000000E1, read32_test
|
||||
|
||||
#test fifo watermark edge cases (wrap arounds, 2s complement)
|
||||
.8byte delay1, 0x00000001, write32_test # reset delay1 register
|
||||
.8byte delay0, 0x00010001, write32_test # reset delay0 register
|
||||
.8byte cs_mode, 0x00000002, write32_test # set cs_mode to hold
|
||||
.8byte tx_data, 0x000000CE, write32_test # place data into tx_data
|
||||
.8byte cs_id, 0x00000001, write32_test #change selected cs pin. should deassert cs[0] in hold mode
|
||||
.8byte cs_def, 0x00001101, write32_test # change selected cs pins def value. should deassert cs[1]
|
||||
.8byte cs_def, 0x00001111, write32_test # reset cs_def
|
||||
.8byte cs_mode, 0x00000000, write32_test # change cs_mode to auto, should deassert cs[1], have now gone through all deassertion conditions
|
||||
.8byte rx_data, 0x000000CE, read32_test # clear rx_fifo
|
||||
|
||||
# =========== Test frame format (fmt) register ===========
|
||||
|
||||
@ -560,12 +607,12 @@ SETUP_PLIC
|
||||
|
||||
.8byte delay1, 0x0000001, write32_test # reset delay1 register
|
||||
.8byte cs_mode, 0x00000000, write32_test # reset cs_mode
|
||||
.8byte tx_mark, 0x00000004, write32_test # set transmit watermark to 4
|
||||
.8byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off)
|
||||
#.8byte ie, 0x00000000, write32_test # enable transmit interrupt
|
||||
.8byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.8byte 0x0, 0x00000000, readmip_test
|
||||
.8byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.8byte ip, 0x00000000, read32_test # tx watermark interupt should be off
|
||||
.8byte ip, 0x00000000, read32_test # tx watermark interupt should be off 125
|
||||
.8byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
@ -584,16 +631,12 @@ SETUP_PLIC
|
||||
.8byte rx_data, 0x00000055, read32_test # clear rx fifo
|
||||
|
||||
|
||||
.8byte tx_mark, 0x00000004, write32_test # set transmit watermark to 4
|
||||
.8byte tx_mark, 0x00000001, write32_test # set transmit watermark to 0
|
||||
.8byte ie, 0x00000001, write32_test # enable transmit interrupt
|
||||
.8byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.8byte 0x0, 0x00000800, readmip_test
|
||||
.8byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.8byte tx_mark, 0x00000001, write32_test
|
||||
.8byte 0x0, 0x00000000, claim_m_plic_interrupts
|
||||
.8byte ip, 0x00000000, read32_test # tx watermark interupt should be off
|
||||
.8byte 0x0, 0x00000000, readmip_test
|
||||
.8byte ie, 0x00000000, write32_test # disable tx intr
|
||||
.8byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.8byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user