Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update README.md

Browse Source
This commit is contained in:
davidharrishmc 2022-01-05 11:29:54 -08:00 committed by GitHub
parent edbaff4ea3
commit d0d9f73794
1 changed files with 1 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
README.md
View File

@ -3,44 +3,4 @@ Configurable RISC-V Processor
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
To use Wally on Linux:
```
git clone https://github.com/davidharrishmc/riscv-wally --recurse-submodules
cd riscv-wally
cd addins
cd riscv-isa-sim
*** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated
cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D
<edit arch_test_target/spike/device/rv64i_m/D/Makefile.include line 35 and change --isa=rv64i to --isa=rv64id>
mkdir build
cd build
set RISCV=/cad/riscv/gcc/bin (or whatever your path is)
../configure --prefix=$RISCV
make (this will take a while to build SPIKE)
sudo make install
cd ../../riscv-arch-test
cp ../riscv-isa-sim/arch_test_target/spike/Makefile.include .
edit Makefile.include
change line with TARGETDIR to /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target (or whatever your path is)
add line export RISCV_PREFIX = riscv64-unknown-elf- # this might not be needed if you have 32-bit versions of the riscv gcc compiler built separately
make
make XLEN=32
exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim
cd ../../tests
cd imperas-riscv-tests
make
cd ../wally-riscv-arch-test
make
make XLEN=32
exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim
cd ../linux-testgen/linux-testvectors
./tvLinker.sh
```
Notes:
Eventually download imperas-riscv-tests separately
Move our custom tests to another directory
Eventually replace exe2memfile.pl with objcopy
See Chapter 2 of draft book of how to install and compile tests.