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More Icache clean up.

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This commit is contained in:
Ross Thompson 2022-01-03 21:22:34 -06:00
parent 2f7cb82c72
commit 89f4b920ff
3 changed files with 1 additions and 11 deletions
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2
wally-pipelined/src/cache/icache.sv vendored
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@ -48,7 +48,6 @@ module icache
// High if the icache is requesting a stall
output logic ICacheStallF,
input logic CacheableF,
input logic ITLBMissF,
input logic InvalidateICacheM,
// The raw (not decompressed) instruction that was requested
@ -159,7 +158,6 @@ module icache
.CPUBusy,
.ICacheMemWriteEnable,
.ICacheStallF,
.ITLBMissF,
.IgnoreRequest,
.ICacheBusAck,
.ICacheFetchLine,

8
wally-pipelined/src/cache/icachefsm.sv vendored
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@ -31,9 +31,6 @@ module icachefsm
input logic CPUBusy,
// inputs from mmu
input logic ITLBMissF,
input logic IgnoreRequest,
input logic CacheableF,
@ -89,11 +86,6 @@ module icachefsm
if(IgnoreRequest) begin
SelAdr = 1'b1;
NextState = STATE_READY;
end else
if(ITLBMissF) begin
NextState = STATE_READY;
SelAdr = 1'b1;
ICacheStallF = 1'b0;
end
else if (CacheableF & hit) begin
ICacheStallF = 1'b0;

2
wally-pipelined/src/ifu/ifu.sv
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@ -247,7 +247,7 @@ module ifu (
generate
if(`MEM_ICACHE) begin : icache
icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
.ICacheBusAdr, .ICacheStallF, .ITLBMissF, .FinalInstrRawF,
.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
.ICacheFetchLine,
.CacheableF,
.PCNextF(PCNextFMux),