mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
Kip Macsai-Goren
commit
e13c050fa1
@ -29,8 +29,8 @@
|
||||
|
||||
rv32i_sc_tests = \
|
||||
WALLY-MMU-SV32 \
|
||||
WALLY-PMA \
|
||||
WALLY-PMP
|
||||
# WALLY-PMA \
|
||||
|
||||
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
||||
|
||||
|
||||
@ -30,8 +30,8 @@
|
||||
rv64i_sc_tests = \
|
||||
WALLY-MMU-SV39 \
|
||||
WALLY-MMU-SV48 \
|
||||
WALLY-PMA \
|
||||
WALLY-PMP
|
||||
# WALLY-PMP
|
||||
# WALLY-PMA \
|
||||
|
||||
|
||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||
|
||||
@ -50,7 +50,7 @@
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_DCACHE 0
|
||||
`define MEM_IROM 1
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 0
|
||||
|
||||
@ -13,7 +13,7 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/Ret
|
||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/IfuStallF
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
|
||||
@ -41,7 +41,7 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/FinalInstrRawF
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
|
||||
@ -170,39 +170,31 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCPF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/ITLBWriteF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/RAdr
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPSpillF
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spill
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave
|
||||
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAdr
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusHRDATA
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/IfuBusAck
|
||||
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/ICacheMemReadData
|
||||
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/icache/SpillDataBlock0
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
|
||||
@ -225,154 +217,148 @@ add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/result
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/srca
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/srcb
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/amo/amoalu/width
|
||||
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/InterlockCurrState
|
||||
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
|
||||
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FinalWriteDataM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/FinalWriteDataM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/MemAdrE_RENAME
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/DCacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/WordCount
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/IgnoreRequest
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/IgnoreRequest
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/LsuPAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FinalWriteDataM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FinalWriteDataM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/WordCount
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheBusAck
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockSetsM
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable
|
||||
@ -382,11 +368,11 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dm
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM
|
||||
@ -396,9 +382,9 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dm
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
vsim -do "do wally-pipelined.do rv64gc imperas64i"
|
||||
vsim -do "do wally-pipelined.do rv64gc arch64d"
|
||||
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
vsim -c <<!
|
||||
do wally-pipelined-batch.do rv64gc wally64priv
|
||||
do wally-pipelined-batch.do rv64gc imperas64i
|
||||
!
|
||||
|
||||
@ -11,7 +11,6 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/Ret
|
||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
|
||||
@ -39,7 +38,7 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/FinalInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
|
||||
@ -157,37 +156,9 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/IfuBusFetch
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/IfuBusFetch
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
|
||||
@ -205,194 +176,182 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/HitPageType
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/InterlockStall
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/LSUStall
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelUncachedAdr
|
||||
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA
|
||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
||||
@ -473,8 +432,37 @@ add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine
|
||||
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine
|
||||
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/busfsm/LsuBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/icachefsm/NextState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ITLBWriteF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPSpillF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spill
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/PreCntEn
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheBusAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheMemWriteEnable
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ICacheMemReadData
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SpillDataBlock0
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||
add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/icache/ICacheFetchLine
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {9745 ns} 0} {{Cursor 4} {49574 ns} 1}
|
||||
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {1239086 ns} 0} {{Cursor 4} {49574 ns} 1}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
@ -490,4 +478,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {9530 ns} {9952 ns}
|
||||
WaveRestoreZoom {1238897 ns} {1239273 ns}
|
||||
|
||||
4
wally-pipelined/src/cache/cacheway.sv
vendored
4
wally-pipelined/src/cache/cacheway.sv
vendored
@ -124,7 +124,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
assign Valid = ValidBits[RAdrD];
|
||||
|
||||
generate
|
||||
if(DIRTY_BITS) begin
|
||||
if(DIRTY_BITS) begin:dirty
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset)
|
||||
DirtyBits <= {NUMLINES{1'b0}};
|
||||
@ -139,7 +139,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
|
||||
assign Dirty = DirtyBits[RAdrD];
|
||||
|
||||
end else begin
|
||||
end else begin:dirty
|
||||
assign Dirty = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
8
wally-pipelined/src/cache/dcache.sv
vendored
8
wally-pipelined/src/cache/dcache.sv
vendored
@ -121,7 +121,7 @@ module dcache
|
||||
|
||||
mux3 #(INDEXLEN)
|
||||
AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** optimize change to virtual address.
|
||||
.d2(FlushAdr),
|
||||
.s(SelAdrM),
|
||||
.y(RAdr));
|
||||
@ -142,7 +142,7 @@ module dcache
|
||||
.InvalidateAll(1'b0));
|
||||
|
||||
generate
|
||||
if(NUMWAYS > 1) begin
|
||||
if(NUMWAYS > 1) begin:vict
|
||||
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
|
||||
cachereplacementpolicy(.clk, .reset,
|
||||
.WayHit,
|
||||
@ -150,7 +150,7 @@ module dcache
|
||||
.LsuPAdrM(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.RAdr,
|
||||
.LRUWriteEn);
|
||||
end else begin
|
||||
end else begin:vict
|
||||
assign VictimWay = 1'b1; // one hot.
|
||||
end
|
||||
endgenerate
|
||||
@ -171,7 +171,7 @@ module dcache
|
||||
// *** consider using a limited range shift to do this final muxing.
|
||||
genvar index;
|
||||
generate
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:readdatablocksetsmux
|
||||
assign ReadDataBlockSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
175
wally-pipelined/src/cache/icache.sv
vendored
175
wally-pipelined/src/cache/icache.sv
vendored
@ -28,28 +28,27 @@
|
||||
module icache
|
||||
(
|
||||
// Basic pipeline stuff
|
||||
input logic clk, reset,
|
||||
input logic CPUBusy,
|
||||
input logic [`PA_BITS-1:0] PCNextF,
|
||||
input logic [`PA_BITS-1:0] PCPF,
|
||||
input logic [`XLEN-1:0] PCF,
|
||||
input logic clk, reset,
|
||||
input logic CPUBusy,
|
||||
input logic [11:0] PCNextF,
|
||||
input logic [`PA_BITS-1:0] PCPF,
|
||||
input logic [`XLEN-1:0] PCF,
|
||||
|
||||
input logic ExceptionM, PendingInterruptM,
|
||||
input logic IgnoreRequest,
|
||||
|
||||
// Data read in from the ebu unit
|
||||
(* mark_debug = "true" *) input logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
(* mark_debug = "true" *) input logic ICacheBusAck,
|
||||
input logic [`ICACHE_BLOCKLENINBITS-1:0] ICacheMemWriteData,
|
||||
output logic ICacheFetchLine,
|
||||
|
||||
(* mark_debug = "true" *) input logic ICacheBusAck,
|
||||
// Read requested from the ebu unit
|
||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr,
|
||||
(* mark_debug = "true" *) output logic IfuBusFetch,
|
||||
// High if the instruction currently in the fetch stage is compressed
|
||||
output logic CompressedF,
|
||||
//output logic CompressedF,
|
||||
// High if the icache is requesting a stall
|
||||
output logic ICacheStallF,
|
||||
input logic CacheableF,
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
input logic InvalidateICacheM,
|
||||
output logic ICacheStallF,
|
||||
input logic CacheableF,
|
||||
input logic InvalidateICacheM,
|
||||
|
||||
// The raw (not decompressed) instruction that was requested
|
||||
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
|
||||
@ -65,41 +64,18 @@ module icache
|
||||
localparam integer INDEXLEN = $clog2(NUMLINES);
|
||||
localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
|
||||
|
||||
// *** not used?
|
||||
localparam WORDSPERLINE = BLOCKLEN/`XLEN;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
|
||||
localparam FetchCountThreshold = WORDSPERLINE - 1;
|
||||
|
||||
localparam integer PA_WIDTH = `PA_BITS - 2;
|
||||
localparam integer NUMWAYS = `ICACHE_NUMWAYS;
|
||||
|
||||
|
||||
// Input signals to cache memory
|
||||
logic ICacheMemWriteEnable;
|
||||
logic [BLOCKLEN-1:0] ICacheMemWriteData;
|
||||
logic [`PA_BITS-1:0] FinalPCPF;
|
||||
// Output signals from cache memory
|
||||
logic [31:0] ICacheMemReadData;
|
||||
logic ICacheReadEn;
|
||||
logic [BLOCKLEN-1:0] ReadLineF;
|
||||
|
||||
|
||||
logic [15:0] SpillDataBlock0;
|
||||
logic spill;
|
||||
logic spillSave;
|
||||
|
||||
logic FetchCountFlag;
|
||||
logic CntEn;
|
||||
|
||||
logic [1:1] SelAdr_q;
|
||||
|
||||
|
||||
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
|
||||
|
||||
logic [`PA_BITS-1:0] PCPSpillF;
|
||||
|
||||
logic CntReset;
|
||||
logic [1:0] SelAdr;
|
||||
logic SelAdr;
|
||||
logic [INDEXLEN-1:0] RAdr;
|
||||
logic [NUMWAYS-1:0] VictimWay;
|
||||
logic LRUWriteEn;
|
||||
@ -111,22 +87,12 @@ module icache
|
||||
|
||||
logic [31:0] ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0];
|
||||
|
||||
logic [`PA_BITS-1:0] BasePAdrMaskedF;
|
||||
logic [OFFSETLEN-1:0] BasePAdrOffsetF;
|
||||
|
||||
|
||||
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
|
||||
|
||||
|
||||
// on spill we want to get the first 2 bytes of the next cache block.
|
||||
// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
|
||||
// simply add 2 to land on the next cache block.
|
||||
assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10};
|
||||
|
||||
mux3 #(INDEXLEN)
|
||||
mux2 #(INDEXLEN)
|
||||
AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(PCF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d2(PCPSpillF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.s(SelAdr),
|
||||
.y(RAdr));
|
||||
|
||||
@ -134,7 +100,7 @@ module icache
|
||||
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
|
||||
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
|
||||
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
|
||||
.PAdr(FinalPCPF),
|
||||
.PAdr(PCPF),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.VDWriteEnable(1'b0),
|
||||
.WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
|
||||
@ -149,15 +115,15 @@ module icache
|
||||
.InvalidateAll(InvalidateICacheM));
|
||||
|
||||
generate
|
||||
if(NUMWAYS > 1) begin
|
||||
if(NUMWAYS > 1) begin:vict
|
||||
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
|
||||
cachereplacementpolicy(.clk, .reset,
|
||||
.WayHit,
|
||||
.VictimWay,
|
||||
.LsuPAdrM(FinalPCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.LsuPAdrM(PCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.RAdr,
|
||||
.LRUWriteEn);
|
||||
end else begin
|
||||
end else begin:vict
|
||||
assign VictimWay = 1'b1; // one hot.
|
||||
end
|
||||
endgenerate
|
||||
@ -171,99 +137,34 @@ module icache
|
||||
|
||||
genvar index;
|
||||
generate
|
||||
for(index = 0; index < BLOCKLEN / 16 - 1; index++) begin
|
||||
for(index = 0; index < BLOCKLEN / 16 - 1; index++) begin:readlinesetsmux
|
||||
assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)];
|
||||
end
|
||||
assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]};
|
||||
endgenerate
|
||||
|
||||
assign ICacheMemReadData = ReadLineSetsF[FinalPCPF[$clog2(BLOCKLEN / 32) + 1 : 1]];
|
||||
assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(BLOCKLEN / 32) + 1 : 1]];
|
||||
|
||||
assign ICacheBusAdr = {PCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};
|
||||
|
||||
// spills require storing the first cache block so it can merged
|
||||
// with the second
|
||||
// can optimize size, for now just make it the size of the data
|
||||
// leaving the cache memory.
|
||||
flopenr #(16) SpillInstrReg(.clk(clk),
|
||||
.en(spillSave),
|
||||
.reset(reset),
|
||||
.d(ICacheMemReadData[15:0]),
|
||||
.q(SpillDataBlock0));
|
||||
|
||||
assign FinalInstrRawF = spill ? {ICacheMemReadData[15:0], SpillDataBlock0} : ICacheMemReadData;
|
||||
|
||||
// Detect if the instruction is compressed
|
||||
assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
|
||||
assign spill = &PCF[$clog2(BLOCKLEN/32)+1:1];
|
||||
|
||||
|
||||
// to compute the fetch address we need to add the bit shifted
|
||||
// counter output to the address.
|
||||
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
|
||||
|
||||
flopenr #(LOGWPL)
|
||||
FetchCountReg(.clk(clk),
|
||||
.reset(reset | CntReset),
|
||||
.en(CntEn),
|
||||
.d(NextFetchCount),
|
||||
.q(FetchCount));
|
||||
|
||||
assign NextFetchCount = FetchCount + 1'b1;
|
||||
|
||||
|
||||
// store read data from memory interface before writing into SRAM.
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer
|
||||
flopenr #(`XLEN) sb(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(ICacheBusAck & (i == FetchCount)),
|
||||
.d(IfuBusHRDATA),
|
||||
.q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
|
||||
// *** read enable may not be necessary.
|
||||
flopenr #(1) SelAdrReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(ICacheReadEn),
|
||||
.d(SelAdr[1]),
|
||||
.q(SelAdr_q[1]));
|
||||
|
||||
assign FinalPCPF = SelAdr_q[1] ? PCPSpillF : PCPF;
|
||||
|
||||
// if not cacheable the offset bits needs to be sent to the EBU.
|
||||
// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
|
||||
assign BasePAdrOffsetF = CacheableF ? {{OFFSETLEN}{1'b0}} : FinalPCPF[OFFSETLEN-1:0];
|
||||
assign BasePAdrMaskedF = {FinalPCPF[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetF};
|
||||
|
||||
assign ICacheBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedF;
|
||||
|
||||
// truncate the offset from PCPF for memory address generation
|
||||
|
||||
assign SRAMWayWriteEnable = ICacheMemWriteEnable ? VictimWay : '0;
|
||||
|
||||
icachefsm controller(.clk,
|
||||
.reset,
|
||||
.CPUBusy,
|
||||
.ICacheReadEn,
|
||||
.ICacheMemWriteEnable,
|
||||
.ICacheStallF,
|
||||
.ITLBMissF,
|
||||
.ITLBWriteF,
|
||||
.ExceptionM,
|
||||
.PendingInterruptM,
|
||||
.ICacheBusAck,
|
||||
.IfuBusFetch,
|
||||
.hit,
|
||||
.FetchCountFlag,
|
||||
.spill,
|
||||
.spillSave,
|
||||
.CntEn,
|
||||
.CntReset,
|
||||
.SelAdr,
|
||||
.LRUWriteEn);
|
||||
|
||||
icachefsm icachefsm(.clk,
|
||||
.reset,
|
||||
.CPUBusy,
|
||||
.ICacheMemWriteEnable,
|
||||
.ICacheStallF,
|
||||
.IgnoreRequest,
|
||||
.ICacheBusAck,
|
||||
.ICacheFetchLine,
|
||||
.CacheableF,
|
||||
.hit,
|
||||
.SelAdr,
|
||||
.LRUWriteEn);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
254
wally-pipelined/src/cache/icachefsm.sv
vendored
254
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -31,22 +31,15 @@ module icachefsm
|
||||
|
||||
input logic CPUBusy,
|
||||
|
||||
// inputs from mmu
|
||||
input logic ITLBMissF,
|
||||
input logic ITLBWriteF,
|
||||
|
||||
input logic ExceptionM, PendingInterruptM,
|
||||
input logic IgnoreRequest,
|
||||
input logic CacheableF,
|
||||
|
||||
// BUS interface
|
||||
input logic ICacheBusAck,
|
||||
|
||||
// icache internal inputs
|
||||
input logic hit,
|
||||
input logic FetchCountFlag,
|
||||
input logic spill,
|
||||
|
||||
// icache internal outputs
|
||||
output logic ICacheReadEn,
|
||||
// Load data into the cache
|
||||
output logic ICacheMemWriteEnable,
|
||||
|
||||
@ -54,59 +47,22 @@ module icachefsm
|
||||
output logic ICacheStallF,
|
||||
|
||||
// Bus interface outputs
|
||||
output logic IfuBusFetch,
|
||||
output logic ICacheFetchLine,
|
||||
|
||||
// icache internal outputs
|
||||
output logic spillSave,
|
||||
output logic CntEn,
|
||||
output logic CntReset,
|
||||
output logic [1:0] SelAdr,
|
||||
output logic SelAdr,
|
||||
output logic LRUWriteEn
|
||||
);
|
||||
|
||||
// FSM states
|
||||
typedef enum {STATE_READY,
|
||||
STATE_HIT_SPILL, // spill, block 0 hit
|
||||
STATE_HIT_SPILL_MISS_FETCH_WDV, // block 1 miss, issue read to AHB and wait data.
|
||||
STATE_HIT_SPILL_MISS_FETCH_DONE, // write data into SRAM/LUT
|
||||
STATE_HIT_SPILL_MERGE, // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
|
||||
|
||||
// a challenge is the spill signal gets us out of the ready state and moves us to
|
||||
// 1 of the 2 spill branches. However the original fsm design had us return to
|
||||
// the ready state when the spill + hits/misses were fully resolved. The problem
|
||||
// is the spill signal is based on PCPF so when we return to READY to check if the
|
||||
// cache has a hit it still expresses spill. We can fix in 1 of two ways.
|
||||
// 1. we can add 1 extra state at the end of each spill branch to returns the instruction
|
||||
// to the CPU advancing the CPU and icache to the next instruction.
|
||||
// 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
|
||||
// to the READY state.
|
||||
// The first first option is more robust and increases the number of states by 2. The
|
||||
// second option is seams like it should work, but I worry there is a hidden interaction
|
||||
// between CPU stalling and that register.
|
||||
// Picking option 1.
|
||||
|
||||
STATE_HIT_SPILL_FINAL, // this state replicates STATE_READY's replay of the
|
||||
// spill access but does nto consider spill. It also does not do another operation.
|
||||
|
||||
STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
|
||||
STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
|
||||
STATE_MISS_READ, // read block 1 from SRAM/LUT
|
||||
STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT
|
||||
|
||||
STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
|
||||
STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
|
||||
STATE_MISS_SPILL_READ1, // read block 0 from SRAM/LUT
|
||||
STATE_MISS_SPILL_2, // return to ready if hit or do second block update.
|
||||
STATE_MISS_SPILL_2_START, // return to ready if hit or do second block update.
|
||||
STATE_MISS_SPILL_MISS_FETCH_WDV, // miss on block 1, issue read to AHB and wait
|
||||
STATE_MISS_SPILL_MISS_FETCH_DONE, // write data to SRAM/LUT
|
||||
STATE_MISS_SPILL_MERGE, // read block 0 of CPU access,
|
||||
|
||||
STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the
|
||||
// spill access but does nto consider spill. It also does not do another operation.
|
||||
|
||||
STATE_CPU_BUSY,
|
||||
STATE_CPU_BUSY_SPILL
|
||||
STATE_CPU_BUSY
|
||||
} statetype;
|
||||
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
@ -119,212 +75,65 @@ module icachefsm
|
||||
|
||||
// Next state logic
|
||||
always_comb begin
|
||||
CntReset = 1'b0;
|
||||
PreCntEn = 1'b0;
|
||||
//IfuBusFetch = 1'b0;
|
||||
ICacheMemWriteEnable = 1'b0;
|
||||
spillSave = 1'b0;
|
||||
SelAdr = 2'b00;
|
||||
ICacheReadEn = 1'b0;
|
||||
SelAdr = 1'b0;
|
||||
ICacheStallF = 1'b1;
|
||||
LRUWriteEn = 1'b0;
|
||||
case (CurrState)
|
||||
STATE_READY: begin
|
||||
SelAdr = 2'b00;
|
||||
ICacheReadEn = 1'b1;
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if (ITLBMissF & ~(ExceptionM | PendingInterruptM)) begin
|
||||
NextState = STATE_TLB_MISS;
|
||||
end else
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
if(ITLBMissF) begin
|
||||
SelAdr = 1'b0;
|
||||
if(IgnoreRequest) begin
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
SelAdr = 2'b01;
|
||||
ICacheStallF = 1'b0;
|
||||
end
|
||||
else if (hit & ~spill) begin
|
||||
else if (CacheableF & hit) begin
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 2'b01;
|
||||
SelAdr = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end else if (hit & spill) begin
|
||||
spillSave = 1'b1;
|
||||
SelAdr = 2'b10;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_HIT_SPILL;
|
||||
end else if (~hit & ~spill) begin
|
||||
CntReset = 1'b1;
|
||||
SelAdr = 2'b01; /// *********(
|
||||
end else if (CacheableF & ~hit) begin
|
||||
SelAdr = 1'b1; /// *********(
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end else if (~hit & spill) begin
|
||||
CntReset = 1'b1;
|
||||
SelAdr = 2'b01;
|
||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||
end else begin
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 2'b01;
|
||||
SelAdr = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
end
|
||||
// branch 1, hit spill and 2, miss spill hit
|
||||
STATE_HIT_SPILL: begin
|
||||
SelAdr = 2'b10;
|
||||
ICacheReadEn = 1'b1;
|
||||
if (hit) begin
|
||||
NextState = STATE_HIT_SPILL_FINAL;
|
||||
end else begin
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_HIT_SPILL_MISS_FETCH_WDV: begin
|
||||
SelAdr = 2'b10;
|
||||
//IfuBusFetch = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_HIT_SPILL_MISS_FETCH_DONE: begin
|
||||
SelAdr = 2'b10;
|
||||
ICacheMemWriteEnable = 1'b1;
|
||||
NextState = STATE_HIT_SPILL_MERGE;
|
||||
end
|
||||
STATE_HIT_SPILL_MERGE: begin
|
||||
SelAdr = 2'b10;
|
||||
ICacheReadEn = 1'b1;
|
||||
NextState = STATE_HIT_SPILL_FINAL;
|
||||
end
|
||||
STATE_HIT_SPILL_FINAL: begin
|
||||
ICacheReadEn = 1'b1;
|
||||
SelAdr = 2'b00;
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_SPILL;
|
||||
SelAdr = 2'b10;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
|
||||
end
|
||||
// branch 3 miss no spill
|
||||
STATE_MISS_FETCH_WDV: begin
|
||||
SelAdr = 2'b01;
|
||||
SelAdr = 1'b1;
|
||||
//IfuBusFetch = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
if (ICacheBusAck) begin
|
||||
NextState = STATE_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_MISS_FETCH_DONE: begin
|
||||
SelAdr = 2'b01;
|
||||
SelAdr = 1'b1;
|
||||
ICacheMemWriteEnable = 1'b1;
|
||||
NextState = STATE_MISS_READ;
|
||||
end
|
||||
STATE_MISS_READ: begin
|
||||
SelAdr = 2'b01;
|
||||
ICacheReadEn = 1'b1;
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_MISS_READ_DELAY;
|
||||
end
|
||||
STATE_MISS_READ_DELAY: begin
|
||||
//SelAdr = 2'b01;
|
||||
ICacheReadEn = 1'b1;
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
SelAdr = 2'b01;
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 2'b01;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
// branch 4 miss spill hit, and 5 miss spill miss
|
||||
STATE_MISS_SPILL_FETCH_WDV: begin
|
||||
SelAdr = 2'b01;
|
||||
PreCntEn = 1'b1;
|
||||
//IfuBusFetch = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
NextState = STATE_MISS_SPILL_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_SPILL_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_MISS_SPILL_FETCH_DONE: begin
|
||||
SelAdr = 2'b01;
|
||||
ICacheMemWriteEnable = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_READ1;
|
||||
end
|
||||
STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
|
||||
SelAdr = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives.
|
||||
ICacheReadEn = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_2;
|
||||
end
|
||||
STATE_MISS_SPILL_2: begin
|
||||
SelAdr = 2'b10;
|
||||
spillSave = 1'b1; /// *** Could pipeline these to make it clearer in the fsm.
|
||||
ICacheReadEn = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_2_START;
|
||||
end
|
||||
STATE_MISS_SPILL_2_START: begin
|
||||
if (~hit) begin
|
||||
CntReset = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
|
||||
end else begin
|
||||
ICacheReadEn = 1'b1;
|
||||
SelAdr = 2'b00;
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_SPILL;
|
||||
SelAdr = 2'b10;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_MISS_SPILL_MISS_FETCH_WDV: begin
|
||||
SelAdr = 2'b10;
|
||||
PreCntEn = 1'b1;
|
||||
//IfuBusFetch = 1'b1;
|
||||
if (FetchCountFlag & ICacheBusAck) begin
|
||||
NextState = STATE_MISS_SPILL_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
STATE_MISS_SPILL_MISS_FETCH_DONE: begin
|
||||
SelAdr = 2'b10;
|
||||
ICacheMemWriteEnable = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_MERGE;
|
||||
end
|
||||
STATE_MISS_SPILL_MERGE: begin
|
||||
SelAdr = 2'b10;
|
||||
ICacheReadEn = 1'b1;
|
||||
NextState = STATE_MISS_SPILL_FINAL;
|
||||
end
|
||||
STATE_MISS_SPILL_FINAL: begin
|
||||
ICacheReadEn = 1'b1;
|
||||
SelAdr = 2'b00;
|
||||
ICacheStallF = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_SPILL;
|
||||
SelAdr = 2'b10;
|
||||
SelAdr = 1'b1;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
@ -333,35 +142,20 @@ module icachefsm
|
||||
ICacheStallF = 1'b0;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY;
|
||||
SelAdr = 2'b01;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
STATE_CPU_BUSY_SPILL: begin
|
||||
ICacheStallF = 1'b0;
|
||||
ICacheReadEn = 1'b1;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_SPILL;
|
||||
SelAdr = 2'b10;
|
||||
SelAdr = 1'b1;
|
||||
end
|
||||
else begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
SelAdr = 2'b01;
|
||||
SelAdr = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
// *** add in error handling and invalidate/evict
|
||||
endcase
|
||||
end
|
||||
|
||||
assign CntEn = PreCntEn & ICacheBusAck;
|
||||
assign IfuBusFetch = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
|
||||
(CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
|
||||
assign ICacheFetchLine = CurrState == STATE_MISS_FETCH_WDV;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -40,10 +40,10 @@ module ahblite (
|
||||
input logic UnsignedLoadM,
|
||||
input logic [1:0] AtomicMaskedM,
|
||||
// Signals from Instruction Cache
|
||||
input logic [`PA_BITS-1:0] ICacheBusAdr, // *** rename these to match block diagram
|
||||
input logic IfuBusFetch,
|
||||
input logic [`PA_BITS-1:0] IfuBusAdr,
|
||||
input logic IfuBusRead,
|
||||
output logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
output logic ICacheBusAck,
|
||||
output logic IfuBusAck,
|
||||
// Signals from Data Cache
|
||||
input logic [`PA_BITS-1:0] LsuBusAdr,
|
||||
input logic LsuBusRead,
|
||||
@ -100,23 +100,23 @@ module ahblite (
|
||||
case (BusState)
|
||||
IDLE: if (LsuBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
|
||||
else if (LsuBusWrite)NextBusState = MEMWRITE;
|
||||
else if (IfuBusFetch) NextBusState = INSTRREAD;
|
||||
else if (IfuBusRead) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE;
|
||||
MEMREAD: if (~HREADY) NextBusState = MEMREAD;
|
||||
else if (IfuBusFetch) NextBusState = INSTRREAD;
|
||||
else if (IfuBusRead) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE;
|
||||
MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
|
||||
else if (IfuBusFetch) NextBusState = INSTRREAD;
|
||||
else if (IfuBusRead) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE;
|
||||
INSTRREAD: if (~HREADY) NextBusState = INSTRREAD;
|
||||
else NextBusState = IDLE; // if (IfuBusFetch still high)
|
||||
else NextBusState = IDLE; // if (IfuBusRead still high)
|
||||
default: NextBusState = IDLE;
|
||||
endcase
|
||||
|
||||
|
||||
// bus outputs
|
||||
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
|
||||
assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : ICacheBusAdr[31:0];
|
||||
assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
|
||||
assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : IfuBusAdr[31:0];
|
||||
assign #1 HADDR = AccessAddress;
|
||||
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
|
||||
assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize;
|
||||
@ -138,7 +138,7 @@ module ahblite (
|
||||
|
||||
assign IfuBusHRDATA = HRDATA;
|
||||
assign LsuBusHRDATA = HRDATA;
|
||||
assign ICacheBusAck = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
|
||||
assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
|
||||
assign IfuBusAck = (BusState == INSTRREAD) & (NextBusState != INSTRREAD);
|
||||
assign LsuBusAck = (BusState == MEMREAD) & (NextBusState != MEMREAD) | (BusState == MEMWRITE) & (NextBusState != MEMWRITE);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -57,11 +57,11 @@ module amoalu (
|
||||
|
||||
// sign extend if necessary
|
||||
generate
|
||||
if (`XLEN == 32) begin
|
||||
if (`XLEN == 32) begin:sext
|
||||
assign a = srca;
|
||||
assign b = srcb;
|
||||
assign result = y;
|
||||
end else begin // `XLEN = 64
|
||||
end else begin:sext // `XLEN = 64
|
||||
always_comb
|
||||
if (width == 2'b10) begin // sign-extend word-length operations
|
||||
// *** it would be more efficient to look at carry out of bit 31 to determine comparisons than do this big mux on and b
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
// `include "wally-config.vh"
|
||||
`include "wally-config.vh"
|
||||
module cvtfp (
|
||||
input logic [10:0] XExpE, // input's exponent
|
||||
input logic [52:0] XManE, // input's mantissa
|
||||
@ -157,15 +157,28 @@ module cvtfp (
|
||||
// Result Selection
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// select the double to single precision result
|
||||
assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} :
|
||||
Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} :
|
||||
Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} :
|
||||
{XSgnE, 8'hff, 23'b0} :
|
||||
{XSgnE, DSResExp, DSResFrac};
|
||||
generate if(`IEEE754) begin
|
||||
// select the double to single precision result
|
||||
assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} :
|
||||
Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} :
|
||||
Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} :
|
||||
{XSgnE, 8'hff, 23'b0} :
|
||||
{XSgnE, DSResExp, DSResFrac};
|
||||
|
||||
// select the final result based on the opperation
|
||||
assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]};
|
||||
// select the final result based on the opperation
|
||||
assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]};
|
||||
end else begin
|
||||
// select the double to single precision result
|
||||
assign DSRes = XNaNE ? {1'b0, {8{1'b1}}, 1'b1, 22'b0} :
|
||||
Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} :
|
||||
Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} :
|
||||
{XSgnE, 8'hff, 23'b0} :
|
||||
{XSgnE, DSResExp, DSResFrac};
|
||||
|
||||
// select the final result based on the opperation
|
||||
assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE&~XNaNE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]&{51{~XNaNE}}};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule // fpadd
|
||||
|
||||
|
||||
@ -1,332 +1,97 @@
|
||||
|
||||
//
|
||||
// File name : fpcomp.v
|
||||
// Title : Floating-Point Comparator
|
||||
// project : FPU
|
||||
// Library : fpcomp
|
||||
// Author(s) : James E. Stine
|
||||
// Purpose : definition of main unit to floating-point comparator
|
||||
// notes :
|
||||
//
|
||||
// Copyright Oklahoma State University
|
||||
//
|
||||
// Floating Point Comparator (Algorithm)
|
||||
//
|
||||
// 1.) Performs sign-extension if the inputs are 32-bit integers.
|
||||
// 2.) Perform a magnitude comparison on the lower 63 bits of the inputs
|
||||
// 3.) Check for special cases (+0=-0, unordered, and infinite values)
|
||||
// and correct for sign bits
|
||||
//
|
||||
// This module takes 64-bits inputs op1 and op2, VSS, and VDD
|
||||
// signals, and a 2-bit signal FOpCtrlE that indicates the type of
|
||||
// operands being compared as indicated below.
|
||||
// FOpCtrlE Description
|
||||
// 00 double precision numbers
|
||||
// 01 single precision numbers
|
||||
// 10 half precision numbers
|
||||
// 11 (unused)
|
||||
//
|
||||
// The comparator produces a 2-bit signal FCC, which
|
||||
// indicates the result of the comparison:
|
||||
//
|
||||
// fcc decscription
|
||||
// 00 A = B
|
||||
// 01 A < B
|
||||
// 10 A > B
|
||||
// 11 A and B are unordered (i.e., A or B is NaN)
|
||||
//
|
||||
// It also produces an invalid operation flag, which is one
|
||||
// if either of the input operands is a signaling NaN per 754
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
// FOpCtrlE values
|
||||
// 111 min
|
||||
// 101 max
|
||||
// 010 equal
|
||||
// 001 less than
|
||||
// 011 less than or equal
|
||||
|
||||
|
||||
module fcmp (
|
||||
input logic [63:0] op1,
|
||||
input logic [63:0] op2,
|
||||
input logic XNaNE, YNaNE,
|
||||
input logic XZeroE, YZeroE,
|
||||
input logic [63:0] FSrcXE,
|
||||
input logic [63:0] FSrcYE,
|
||||
input logic [2:0] FOpCtrlE,
|
||||
input logic FmtE,
|
||||
input logic FmtE, // precision 1 = double 0 = single
|
||||
input logic [2:0] FOpCtrlE, // see above table
|
||||
input logic XSgnE, YSgnE, // input signs
|
||||
input logic [`NE-1:0] XExpE, YExpE, // input exponents
|
||||
input logic [`NF:0] XManE, YManE, // input mantissa
|
||||
input logic XZeroE, YZeroE, // is zero
|
||||
input logic XNaNE, YNaNE, // is NaN
|
||||
input logic XSNaNE, YSNaNE, // is signaling NaN
|
||||
input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs
|
||||
output logic CmpNVE, // invalid flag
|
||||
output logic [`FLEN-1:0] CmpResE // compare resilt
|
||||
);
|
||||
|
||||
|
||||
output logic Invalid, // Invalid Operation
|
||||
output logic [63:0] CmpResE);
|
||||
logic LT, EQ; // is X < or > or = Y
|
||||
|
||||
// Perform magnitude comparison between the 63 least signficant bits
|
||||
// of the input operands. Only LT and EQ are returned, since GT can
|
||||
// be determined from these values.
|
||||
logic [1:0] FCC; // Condition Codes
|
||||
logic [7:0] w, x;
|
||||
// logic ANaN, BNaN;
|
||||
// logic Azero, Bzero;
|
||||
logic LT; // magnitude op1 < magnitude op2
|
||||
logic EQ; // magnitude op1 = magnitude op2
|
||||
// X is less than Y:
|
||||
// Signs:
|
||||
// X Y answer
|
||||
// pos pos idk - keep checking
|
||||
// pos neg no
|
||||
// neg pos yes
|
||||
// neg neg idk - keep checking
|
||||
// Exponent
|
||||
// - if XExp < YExp
|
||||
// - if negitive - no
|
||||
// - if positive - yes
|
||||
// - otherwise keep checking
|
||||
// Mantissa
|
||||
// - XMan < YMan then
|
||||
// - if negitive - no
|
||||
// - if positive - yes
|
||||
// note: LT does -0 < 0
|
||||
assign LT = XSgnE^YSgnE ? XSgnE : XExpE==YExpE ? ((XManE<YManE)^XSgnE)&~EQ : (XExpE<YExpE)^XSgnE;
|
||||
assign EQ = (FSrcXE == FSrcYE);
|
||||
|
||||
// flags
|
||||
// Min/Max - if an input is a signaling NaN set invalid flag
|
||||
// LT/LE - signaling - sets invalid if NaN input
|
||||
// EQ - quiet - sets invalid if signaling NaN input
|
||||
always_comb begin
|
||||
case (FOpCtrlE[2:0])
|
||||
3'b111: CmpNVE = XSNaNE|YSNaNE;//min
|
||||
3'b101: CmpNVE = XSNaNE|YSNaNE;//max
|
||||
3'b010: CmpNVE = XSNaNE|YSNaNE;//equal
|
||||
3'b001: CmpNVE = XNaNE|YNaNE;//less than
|
||||
3'b011: CmpNVE = XNaNE|YNaNE;//less than or equal
|
||||
default: CmpNVE = 1'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
magcompare64b_1 magcomp1 (w, x, {~op1[63], op1[62:0]}, {~op2[63], op2[62:0]});
|
||||
// Min/Max
|
||||
// - outputs the min/max of X and Y
|
||||
// - -0 < 0
|
||||
// - if both are NaN return quiet X
|
||||
// - if one is a NaN output the non-NaN
|
||||
// LT/LE/EQ
|
||||
// - -0 = 0
|
||||
// - inf = inf and -inf = -inf
|
||||
// - return 0 if comparison with NaN (unordered)
|
||||
|
||||
// Determine final values based on output of magnitude comparison,
|
||||
// sign bits, and special case testing.
|
||||
|
||||
// Perform magnitude comparison between the 63 least signficant bits
|
||||
// of the input operands. Only LT and EQ are returned, since GT can
|
||||
// be determined from these values.
|
||||
magcompare64b_2 magcomp2 (LT, EQ, w, x);
|
||||
|
||||
// Determine final values based on output of magnitude comparison,
|
||||
// sign bits, and special case testing.
|
||||
exception_cmp_2 exc2 (
|
||||
.invalid(Invalid), .fcc(FCC), .LT_mag(LT), .EQ_mag(EQ),
|
||||
.ANaN(XNaNE), .BNaN(YNaNE), .Azero(XZeroE), .Bzero(YZeroE),
|
||||
.FOpCtrlE, .A(op1), .B(op2), .FSrcXE, .FSrcYE,
|
||||
.FmtE, .CmpResE
|
||||
);
|
||||
|
||||
endmodule // fpcomp
|
||||
|
||||
|
||||
// 2-bit magnitude comparator
|
||||
// This module compares two 2-bit values A and B. LT is '1' if A < B
|
||||
// and GT is '1'if A > B. LT and GT are both '0' if A = B. However,
|
||||
// this version actually incorporates don't cares into the equation to
|
||||
// simplify the optimization
|
||||
|
||||
module magcompare2c (LT, GT, A, B);
|
||||
|
||||
input logic [1:0] A;
|
||||
input logic [1:0] B;
|
||||
|
||||
output logic LT;
|
||||
output logic GT;
|
||||
|
||||
assign LT = B[1] | (!A[1]&B[0]);
|
||||
assign GT = A[1] | (!B[1]&A[0]);
|
||||
|
||||
endmodule // magcompare2b
|
||||
|
||||
// This module compares two 64-bit values A and B. LT is '1' if A < B
|
||||
// and EQ is '1'if A = B. LT and GT are both '0' if A > B.
|
||||
// This structure was modified so
|
||||
// that it only does a strict magnitdude comparison, and only
|
||||
// returns flags for less than (LT) and eqaual to (EQ). It uses a tree
|
||||
// of 63 2-bit magnitude comparators, followed by one OR gates.
|
||||
//
|
||||
// J. E. Stine and M. J. Schulte, "A combined two's complement and
|
||||
// floating-point comparator," 2005 IEEE International Symposium on
|
||||
// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1.
|
||||
// doi: 10.1109/ISCAS.2005.1464531
|
||||
|
||||
module magcompare64b_1 (w, x, A, B);
|
||||
|
||||
input logic [63:0] A;
|
||||
input logic [63:0] B;
|
||||
|
||||
logic [31:0] s;
|
||||
logic [31:0] t;
|
||||
logic [15:0] u;
|
||||
logic [15:0] v;
|
||||
output logic [7:0] w;
|
||||
output logic [7:0] x;
|
||||
|
||||
magcompare2b mag1(s[0], t[0], A[1:0], B[1:0]);
|
||||
magcompare2b mag2(s[1], t[1], A[3:2], B[3:2]);
|
||||
magcompare2b mag3(s[2], t[2], A[5:4], B[5:4]);
|
||||
magcompare2b mag4(s[3], t[3], A[7:6], B[7:6]);
|
||||
magcompare2b mag5(s[4], t[4], A[9:8], B[9:8]);
|
||||
magcompare2b mag6(s[5], t[5], A[11:10], B[11:10]);
|
||||
magcompare2b mag7(s[6], t[6], A[13:12], B[13:12]);
|
||||
magcompare2b mag8(s[7], t[7], A[15:14], B[15:14]);
|
||||
magcompare2b mag9(s[8], t[8], A[17:16], B[17:16]);
|
||||
magcompare2b magA(s[9], t[9], A[19:18], B[19:18]);
|
||||
magcompare2b magB(s[10], t[10], A[21:20], B[21:20]);
|
||||
magcompare2b magC(s[11], t[11], A[23:22], B[23:22]);
|
||||
magcompare2b magD(s[12], t[12], A[25:24], B[25:24]);
|
||||
magcompare2b magE(s[13], t[13], A[27:26], B[27:26]);
|
||||
magcompare2b magF(s[14], t[14], A[29:28], B[29:28]);
|
||||
magcompare2b mag10(s[15], t[15], A[31:30], B[31:30]);
|
||||
magcompare2b mag11(s[16], t[16], A[33:32], B[33:32]);
|
||||
magcompare2b mag12(s[17], t[17], A[35:34], B[35:34]);
|
||||
magcompare2b mag13(s[18], t[18], A[37:36], B[37:36]);
|
||||
magcompare2b mag14(s[19], t[19], A[39:38], B[39:38]);
|
||||
magcompare2b mag15(s[20], t[20], A[41:40], B[41:40]);
|
||||
magcompare2b mag16(s[21], t[21], A[43:42], B[43:42]);
|
||||
magcompare2b mag17(s[22], t[22], A[45:44], B[45:44]);
|
||||
magcompare2b mag18(s[23], t[23], A[47:46], B[47:46]);
|
||||
magcompare2b mag19(s[24], t[24], A[49:48], B[49:48]);
|
||||
magcompare2b mag1A(s[25], t[25], A[51:50], B[51:50]);
|
||||
magcompare2b mag1B(s[26], t[26], A[53:52], B[53:52]);
|
||||
magcompare2b mag1C(s[27], t[27], A[55:54], B[55:54]);
|
||||
magcompare2b mag1D(s[28], t[28], A[57:56], B[57:56]);
|
||||
magcompare2b mag1E(s[29], t[29], A[59:58], B[59:58]);
|
||||
magcompare2b mag1F(s[30], t[30], A[61:60], B[61:60]);
|
||||
magcompare2b mag20(s[31], t[31], A[63:62], B[63:62]);
|
||||
|
||||
magcompare2c mag21(u[0], v[0], t[1:0], s[1:0]);
|
||||
magcompare2c mag22(u[1], v[1], t[3:2], s[3:2]);
|
||||
magcompare2c mag23(u[2], v[2], t[5:4], s[5:4]);
|
||||
magcompare2c mag24(u[3], v[3], t[7:6], s[7:6]);
|
||||
magcompare2c mag25(u[4], v[4], t[9:8], s[9:8]);
|
||||
magcompare2c mag26(u[5], v[5], t[11:10], s[11:10]);
|
||||
magcompare2c mag27(u[6], v[6], t[13:12], s[13:12]);
|
||||
magcompare2c mag28(u[7], v[7], t[15:14], s[15:14]);
|
||||
magcompare2c mag29(u[8], v[8], t[17:16], s[17:16]);
|
||||
magcompare2c mag2A(u[9], v[9], t[19:18], s[19:18]);
|
||||
magcompare2c mag2B(u[10], v[10], t[21:20], s[21:20]);
|
||||
magcompare2c mag2C(u[11], v[11], t[23:22], s[23:22]);
|
||||
magcompare2c mag2D(u[12], v[12], t[25:24], s[25:24]);
|
||||
magcompare2c mag2E(u[13], v[13], t[27:26], s[27:26]);
|
||||
magcompare2c mag2F(u[14], v[14], t[29:28], s[29:28]);
|
||||
magcompare2c mag30(u[15], v[15], t[31:30], s[31:30]);
|
||||
|
||||
magcompare2c mag31(w[0], x[0], v[1:0], u[1:0]);
|
||||
magcompare2c mag32(w[1], x[1], v[3:2], u[3:2]);
|
||||
magcompare2c mag33(w[2], x[2], v[5:4], u[5:4]);
|
||||
magcompare2c mag34(w[3], x[3], v[7:6], u[7:6]);
|
||||
magcompare2c mag35(w[4], x[4], v[9:8], u[9:8]);
|
||||
magcompare2c mag36(w[5], x[5], v[11:10], u[11:10]);
|
||||
magcompare2c mag37(w[6], x[6], v[13:12], u[13:12]);
|
||||
magcompare2c mag38(w[7], x[7], v[15:14], u[15:14]);
|
||||
|
||||
endmodule // magcompare64b
|
||||
|
||||
// This module compares two 64-bit values A and B. LT is '1' if A < B
|
||||
// and EQ is '1'if A = B. LT and GT are both '0' if A > B.
|
||||
// This structure was modified so
|
||||
// that it only does a strict magnitdude comparison, and only
|
||||
// returns flags for less than (LT) and eqaual to (EQ). It uses a tree
|
||||
// of 63 2-bit magnitude comparators, followed by one OR gates.
|
||||
//
|
||||
// J. E. Stine and M. J. Schulte, "A combined two's complement and
|
||||
// floating-point comparator," 2005 IEEE International Symposium on
|
||||
// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1.
|
||||
// doi: 10.1109/ISCAS.2005.1464531
|
||||
|
||||
module magcompare64b_2 (LT, EQ, w, x);
|
||||
|
||||
input logic [7:0] w;
|
||||
input logic [7:0] x;
|
||||
logic [3:0] y;
|
||||
logic [3:0] z;
|
||||
logic [1:0] a;
|
||||
logic [1:0] b;
|
||||
logic GT;
|
||||
|
||||
output logic LT;
|
||||
output logic EQ;
|
||||
|
||||
magcompare2c mag39(y[0], z[0], x[1:0], w[1:0]);
|
||||
magcompare2c mag3A(y[1], z[1], x[3:2], w[3:2]);
|
||||
magcompare2c mag3B(y[2], z[2], x[5:4], w[5:4]);
|
||||
magcompare2c mag3C(y[3], z[3], x[7:6], w[7:6]);
|
||||
|
||||
magcompare2c mag3D(a[0], b[0], z[1:0], y[1:0]);
|
||||
magcompare2c mag3E(a[1], b[1], z[3:2], y[3:2]);
|
||||
|
||||
magcompare2c mag3F(LT, GT, b[1:0], a[1:0]);
|
||||
|
||||
assign EQ = ~(LT | GT);
|
||||
|
||||
endmodule // magcompare64b
|
||||
|
||||
// This module takes 64-bits inputs A and B, two magnitude comparison
|
||||
// flags LT_mag and EQ_mag, and a 2-bit signal FOpCtrlE that indicates the type of
|
||||
// operands being compared as indicated below.
|
||||
// FOpCtrlE Description
|
||||
// 00 double precision numbers
|
||||
// 01 single precision numbers
|
||||
// 10 half precision numbers
|
||||
// 11 bfloat precision numbers
|
||||
//
|
||||
// The comparator produces a 2-bit signal fcc, which
|
||||
// indicates the result of the comparison as follows:
|
||||
// fcc decscription
|
||||
// 00 A = B
|
||||
// 01 A < B
|
||||
// 10 A > B
|
||||
// 11 A and B are unordered (i.e., A or B is NaN)
|
||||
// It also produces a invalid operation flag, which is one
|
||||
// if either of the input operands is a signaling NaN.
|
||||
|
||||
module exception_cmp_2 (
|
||||
input logic [63:0] A,
|
||||
input logic [63:0] B,
|
||||
input logic [63:0] FSrcXE,
|
||||
input logic [63:0] FSrcYE,
|
||||
input logic FmtE,
|
||||
input logic LT_mag,
|
||||
input logic EQ_mag,
|
||||
input logic [2:0] FOpCtrlE,
|
||||
|
||||
output logic invalid,
|
||||
output logic [1:0] fcc,
|
||||
output logic [63:0] CmpResE,
|
||||
|
||||
input logic Azero,
|
||||
input logic Bzero,
|
||||
input logic ANaN,
|
||||
input logic BNaN);
|
||||
|
||||
logic dp;
|
||||
logic sp;
|
||||
logic hp;
|
||||
logic ASNaN;
|
||||
logic BSNaN;
|
||||
logic UO;
|
||||
logic GT;
|
||||
logic LT;
|
||||
logic EQ;
|
||||
|
||||
assign dp = !FOpCtrlE[1]&!FOpCtrlE[0];
|
||||
assign sp = !FOpCtrlE[1]&FOpCtrlE[0];
|
||||
assign hp = FOpCtrlE[1]&!FOpCtrlE[0];
|
||||
|
||||
// Values are unordered if ((A is NaN) OR (B is NaN)) AND (a floating
|
||||
// point comparison is being performed.
|
||||
assign UO = (ANaN | BNaN);
|
||||
|
||||
// Test if A or B is a signaling NaN.
|
||||
assign ASNaN = ANaN & (sp&~A[53] | dp&~A[50] | hp&~A[56]);
|
||||
assign BSNaN = BNaN & (sp&~B[53] | dp&~B[50] | hp&~B[56]);
|
||||
|
||||
// If either A or B is a signaling NaN the "Invalid Operation"
|
||||
// exception flag is set to one; otherwise it is zero.
|
||||
assign invalid = (ASNaN | BSNaN);
|
||||
|
||||
// A and B are equal if (their magnitudes are equal) AND ((their signs are
|
||||
// equal) or (their magnitudes are zero AND they are floating point
|
||||
// numbers)). Also, A and B are not equal if they are unordered.
|
||||
assign EQ = (EQ_mag | (Azero&Bzero)) & (~UO);
|
||||
|
||||
// A is less than B if (A is negative and B is posiive) OR
|
||||
// (A and B are positive and the magnitude of A is less than
|
||||
// the magnitude of B) or (A and B are negative integers and
|
||||
// the magnitude of A is less than the magnitude of B) or
|
||||
// (A and B are negative floating point numbers and
|
||||
// the magnitude of A is greater than the magnitude of B).
|
||||
// Also, A is not less than B if A and B are equal or unordered.
|
||||
assign LT = ((~LT_mag & A[63] & B[63]) |
|
||||
(LT_mag & ~(A[63] & B[63])))&~EQ&~UO;
|
||||
|
||||
// A is greater than B when LT, EQ, and UO are are false.
|
||||
assign GT = ~(LT | EQ | UO);
|
||||
|
||||
// Note: it may be possible to optimize the setting of fcc
|
||||
// a little more, but it is probably not worth the effort.
|
||||
|
||||
// Set the bits of fcc based on LT, GT, EQ, and UO
|
||||
assign fcc[0] = LT | UO;
|
||||
assign fcc[1] = GT | UO;
|
||||
logic [`FLEN-1:0] QNaNX, QNaNY;
|
||||
generate if(`IEEE754) begin
|
||||
assign QNaNX = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]};
|
||||
assign QNaNY = FmtE ? {YSgnE, YExpE, 1'b1, YManE[`NF-2:0]} : {{32{1'b1}}, YSgnE, YExpE[7:0], 1'b1, YManE[50:29]};
|
||||
end else begin
|
||||
assign QNaNX = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0};
|
||||
assign QNaNY = FmtE ? {1'b0, YExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpE[7:0], 1'b1, 22'b0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always_comb begin
|
||||
case (FOpCtrlE[2:0])
|
||||
3'b111: CmpResE = LT ? FSrcXE : FSrcYE;//min
|
||||
3'b101: CmpResE = GT ? FSrcXE : FSrcYE;//max
|
||||
3'b010: CmpResE = {63'b0, EQ};//equal
|
||||
3'b001: CmpResE = {63'b0, LT};//less than
|
||||
3'b011: CmpResE = {63'b0, LT|EQ};//less than or equal
|
||||
3'b111: CmpResE = XNaNE ? YNaNE ? QNaNX : FSrcYE // Min
|
||||
: YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE;
|
||||
3'b101: CmpResE = XNaNE ? YNaNE ? QNaNX : FSrcYE // Max
|
||||
: YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE;
|
||||
3'b010: CmpResE = {63'b0, (EQ|(XZeroE&YZeroE))&~(XNaNE|YNaNE)}; // Equal
|
||||
3'b001: CmpResE = {63'b0, LT&~(XZeroE&YZeroE)&~(XNaNE|YNaNE)}; // Less than
|
||||
3'b011: CmpResE = {63'b0, (LT|EQ|(XZeroE&YZeroE))&~(XNaNE|YNaNE)}; // Less than or equal
|
||||
default: CmpResE = 64'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule // exception_cmp
|
||||
|
||||
endmodule
|
||||
|
||||
@ -55,9 +55,9 @@ module fctrl (
|
||||
default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction
|
||||
endcase
|
||||
7'b10100??: case(Funct3D)
|
||||
3'b010: ControlsD = `FCTRLW'b0_1_11_010_000_00_0_0; // feq
|
||||
3'b001: ControlsD = `FCTRLW'b0_1_11_001_000_00_0_0; // flt
|
||||
3'b000: ControlsD = `FCTRLW'b0_1_11_011_000_00_0_0; // fle
|
||||
3'b010: ControlsD = `FCTRLW'b0_1_11_010_010_00_0_0; // feq
|
||||
3'b001: ControlsD = `FCTRLW'b0_1_11_001_010_00_0_0; // flt
|
||||
3'b000: ControlsD = `FCTRLW'b0_1_11_011_010_00_0_0; // fle
|
||||
default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction
|
||||
endcase
|
||||
7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_11_000_000_10_0_0; // fclass
|
||||
|
||||
@ -21,7 +21,7 @@ module fcvt (
|
||||
logic ResSgn; // FP result's sign
|
||||
logic [10:0] ResExp,TmpExp; // FP result's exponent
|
||||
logic [51:0] ResFrac; // FP result's fraction
|
||||
logic [5:0] LZResP; // lz output
|
||||
logic [6:0] LZResP; // lz output
|
||||
logic [7:0] Bits; // how many bits are in the integer result
|
||||
logic [7:0] SubBits; // subtract these bits from the exponent (FP result)
|
||||
logic [64+51:0] ShiftedManTmp; // Shifted mantissa
|
||||
@ -42,6 +42,7 @@ module fcvt (
|
||||
logic Res64, In64; // is the result or input 64 bits
|
||||
logic RoundMSB; // most significant bit of the fraction
|
||||
logic RoundSgn; // sign of the rounded result
|
||||
logic Invalid, Inexact; // flags
|
||||
|
||||
// FOpCtrlE:
|
||||
// fcvt.w.s = 001
|
||||
@ -78,7 +79,7 @@ module fcvt (
|
||||
// make the integer positive
|
||||
assign PosInt = IntIn[64-1]&~FOpCtrlE[1] ? -IntIn : IntIn;
|
||||
// determine the integer's sign
|
||||
assign ResSgn = ~FOpCtrlE[1] ? IntIn[64-1] : 1'b0;
|
||||
assign ResSgn = ~FOpCtrlE[1]&IntIn[64-1];
|
||||
|
||||
// Leading one detector
|
||||
logic [8:0] i;
|
||||
@ -89,7 +90,7 @@ module fcvt (
|
||||
end
|
||||
|
||||
// if no one was found set to zero otherwise calculate the exponent
|
||||
assign TmpExp = i==`XLEN ? 0 : FmtE ? 11'd1023 + {3'b0, SubBits} - {5'b0, LZResP} : 11'd127 + {3'b0, SubBits} - {5'b0, LZResP};
|
||||
assign TmpExp = i==`XLEN ? 0 : FmtE ? 11'd1023 + {3'b0, SubBits} - {4'b0, LZResP} : 11'd127 + {3'b0, SubBits} - {4'b0, LZResP};
|
||||
|
||||
|
||||
|
||||
@ -98,7 +99,7 @@ module fcvt (
|
||||
|
||||
|
||||
// select the shift value and amount based on operation (to fp or int)
|
||||
assign ShiftCnt = FOpCtrlE[0] ? ExpVal : {7'b0, LZResP};
|
||||
assign ShiftCnt = FOpCtrlE[0] ? ExpVal : {6'b0, LZResP};
|
||||
assign ShiftVal = FOpCtrlE[0] ? {{64-1{1'b0}}, XManE} : {PosInt, 52'b0};
|
||||
|
||||
// if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds)
|
||||
@ -159,8 +160,8 @@ module fcvt (
|
||||
|
||||
// select the integer result
|
||||
assign CvtIntRes = Of ? FOpCtrlE[1] ? {64{1'b1}} : SgnRes ? {33'b0, {31{1'b1}}}: {1'b0, {63{1'b1}}} :
|
||||
Uf ? FOpCtrlE[1] ? {63'b0, Plus1&~XSgnE} : SgnRes ? {32'b0, 1'b1, 31'b0} : {1'b1, 63'b0} :
|
||||
Rounded[64-1:0];
|
||||
Uf ? FOpCtrlE[1] ? {63'b0, Plus1&~XSgnE} : SgnRes ? {{33{1'b1}}, 31'b0} : {1'b1, 63'b0} :
|
||||
|RoundedTmp ? Rounded[64-1:0] : 64'b0;
|
||||
|
||||
// select the floating point result
|
||||
assign CvtFPRes = FmtE ? {ResSgn, ResExp, ResFrac} : {{32{1'b1}}, ResSgn, ResExp[7:0], ResFrac[51:29]};
|
||||
@ -169,15 +170,19 @@ module fcvt (
|
||||
assign CvtResE = FOpCtrlE[0] ? CvtIntRes : CvtFPRes;
|
||||
|
||||
// calculate the flags
|
||||
// - only set invalid flag for out-of-range vales if it isn't be indicated by the inexact
|
||||
// - don't set inexact flag if converting a really large number (closest __ bit integer value is the max value)
|
||||
// - don't set inexact flag if converting negitive or tiny number to unsigned (closest integer value is 0 or 1)
|
||||
logic Invalid, Inexact;
|
||||
assign Invalid = (Of | Uf)&FOpCtrlE[0];
|
||||
assign Inexact = (Guard|Round|Sticky)&~((&FOpCtrlE[1:0]&Uf&~(Plus1&~XSgnE))|(FOpCtrlE[0]&Of));
|
||||
assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
|
||||
// assign CvtFlgE = {(Of | Uf)&FOpCtrlE[0], 3'b0, (Guard|Round|Sticky)&~FOpCtrlE[0]};
|
||||
// - only set invalid flag for out-of-range vales
|
||||
// - set inexact if in representable range and not exact
|
||||
|
||||
generate if(`IEEE754) begin // checks before rounding
|
||||
assign Invalid = (Of | Uf)&FOpCtrlE[0];
|
||||
assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&(XSgnE|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
|
||||
assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
|
||||
end else begin // RISC-V checks if the result is in range after rounding
|
||||
assign Invalid = (Of | Uf)&FOpCtrlE[0];
|
||||
assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&((XSgnE&~(ShiftCnt[12]&~Plus1))|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
|
||||
assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
|
||||
@ -24,17 +24,18 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
// `define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
|
||||
// `define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
|
||||
// `define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
|
||||
// `define XLEN 64
|
||||
// `define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
|
||||
// `define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
|
||||
// `define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
|
||||
// `define XLEN 64
|
||||
// `define IEEE754 1
|
||||
module fma(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic FlushM, // flush the memory stage
|
||||
input logic StallM, // stall memory stage
|
||||
input logic FmtE, FmtM, // precision 1 = double 0 = single
|
||||
input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
|
||||
input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
|
||||
input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
|
||||
input logic XSgnE, YSgnE, ZSgnE, // input signs - execute stage
|
||||
input logic [`NE-1:0] XExpE, YExpE, ZExpE, // input exponents - execute stage
|
||||
@ -70,6 +71,7 @@ module fma(
|
||||
logic ZSgnEffE, ZSgnEffM;
|
||||
logic PSgnE, PSgnM;
|
||||
logic [8:0] NormCntE, NormCntM;
|
||||
logic Mult;
|
||||
|
||||
fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
|
||||
.XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
|
||||
@ -79,13 +81,13 @@ module fma(
|
||||
// E/M pipeline registers
|
||||
flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM);
|
||||
flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM);
|
||||
flopenrc #(15) EMRegFma4(clk, reset, FlushM, ~StallM,
|
||||
{AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE},
|
||||
{AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM});
|
||||
flopenrc #(16) EMRegFma4(clk, reset, FlushM, ~StallM,
|
||||
{AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0]},
|
||||
{AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult});
|
||||
|
||||
fma2 fma2(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM,
|
||||
.FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .SumM, .NegSumM, .InvZM, .NormCntM, .ZSgnEffM, .PSgnM,
|
||||
.XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM,
|
||||
.XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .Mult,
|
||||
.FMAResM, .FMAFlgM);
|
||||
|
||||
endmodule
|
||||
@ -420,6 +422,7 @@ module fma2(
|
||||
input logic InvZM, // do you invert Z
|
||||
input logic ZSgnEffM, // the modified Z sign - depends on instruction
|
||||
input logic PSgnM, // the product's sign
|
||||
input logic Mult, // multiply opperation
|
||||
input logic [8:0] NormCntM, // the normalization shift count
|
||||
output logic [`FLEN-1:0] FMAResM, // FMA final result
|
||||
output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact}
|
||||
@ -479,7 +482,7 @@ module fma2(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
resultsign resultsign(.FrmM, .PSgnM, .ZSgnEffM, .Underflow, .InvZM, .NegSumM, .SumZero, .ResultSgnTmp, .ResultSgn);
|
||||
resultsign resultsign(.FrmM, .PSgnM, .ZSgnEffM, .Underflow, .InvZM, .NegSumM, .SumZero, .Mult, .ResultSgnTmp, .ResultSgn);
|
||||
|
||||
|
||||
|
||||
@ -515,6 +518,7 @@ module resultsign(
|
||||
input logic InvZM,
|
||||
input logic NegSumM,
|
||||
input logic SumZero,
|
||||
input logic Mult,
|
||||
output logic ResultSgnTmp,
|
||||
output logic ResultSgn
|
||||
);
|
||||
@ -524,8 +528,9 @@ module resultsign(
|
||||
|
||||
// Determine the sign if the sum is zero
|
||||
// if cancelation then 0 unless round to -infinity
|
||||
// if multiply then Psgn
|
||||
// otherwise psign
|
||||
assign ZeroSgn = (PSgnM^ZSgnEffM)&~Underflow ? FrmM[1:0] == 2'b10 : PSgnM;
|
||||
assign ZeroSgn = (PSgnM^ZSgnEffM)&~Underflow&~Mult ? FrmM[1:0] == 2'b10 : PSgnM;
|
||||
|
||||
// is the result negitive
|
||||
// if p - z is the Sum negitive
|
||||
@ -607,8 +612,8 @@ module normalize(
|
||||
assign UfSticky = AddendStickyM | NormSumSticky;
|
||||
|
||||
// Determine sum's exponent
|
||||
// if plus1 If plus2 if said denorm but norm plus 1 if said denorm (-1 val) but norm plus 2
|
||||
assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}+{11'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM, 1'b0}) & {`NE+2{~(SumZero|ResultDenorm)}};
|
||||
// if plus1 If plus2 if said denorm but norm plus 1 if said denorm but norm plus 2
|
||||
assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~ResultDenorm&PreResultDenorm2&~KillProdM}+{12'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}};
|
||||
// recalculate if the result is denormalized
|
||||
assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
|
||||
|
||||
@ -809,14 +814,17 @@ module resultselect(
|
||||
);
|
||||
logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
|
||||
|
||||
generate if(`IEEE754) begin
|
||||
generate
|
||||
if(`IEEE754) begin:nan
|
||||
assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
|
||||
assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
|
||||
assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
|
||||
end else begin
|
||||
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
end else begin:nan
|
||||
assign XNaNResult = FmtM ? {1'b0, XExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpM[7:0], 1'b1, 22'b0};
|
||||
assign YNaNResult = FmtM ? {1'b0, YExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpM[7:0], 1'b1, 22'b0};
|
||||
assign ZNaNResult = FmtM ? {1'b0, ZExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, ZExpM[7:0], 1'b1, 22'b0};
|
||||
assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, 1'b0, 8'hff, 1'b1, 22'b0};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
@ -825,7 +833,6 @@ module resultselect(
|
||||
{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
|
||||
((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} :
|
||||
{{32{1'b1}}, ResultSgn, 8'hff, 23'b0};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} + (RoundAdd[59:29]&{31{AddendStickyM}})};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {63'b0,(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign FMAResM = XNaNM ? XNaNResult :
|
||||
|
||||
@ -116,7 +116,6 @@ module fpu (
|
||||
logic [63:0] CmpResE; // compare result
|
||||
logic CmpNVE; // compare invalid flag (Not Valid)
|
||||
logic [63:0] SgnResE; // sign injection result
|
||||
logic SgnNVE; // sign injection invalid flag (Not Valid)
|
||||
logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage
|
||||
logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage
|
||||
logic [`XLEN-1:0] FIntResE;
|
||||
@ -213,14 +212,12 @@ module fpu (
|
||||
// - computation is done in one stage
|
||||
// - writes to FP file durring min/max instructions
|
||||
// - other comparisons write a 1 or 0 to the integer register
|
||||
fcmp fcmp (.op1({XSgnE,XExpE,XManE[`NF-1:0]}), .op2({YSgnE,YExpE,YManE[`NF-1:0]}),
|
||||
.FSrcXE, .FSrcYE, .FOpCtrlE,
|
||||
.FmtE, .XNaNE, .YNaNE, .XZeroE, .YZeroE,
|
||||
.Invalid(CmpNVE), .CmpResE);
|
||||
fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE,
|
||||
.XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE);
|
||||
|
||||
// sign injection unit
|
||||
fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE,
|
||||
.SgnNVE, .SgnResE);
|
||||
.SgnResE);
|
||||
|
||||
// classify
|
||||
fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE,
|
||||
@ -240,7 +237,7 @@ module fpu (
|
||||
|
||||
// select a result that may be written to the FP register
|
||||
mux5 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE);
|
||||
mux5 #(5) FFlgMux(5'b0, {4'b0, SgnNVE}, {4'b0, CmpNVE}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE);
|
||||
mux5 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE);
|
||||
|
||||
// select the result that may be written to the integer register - to IEU
|
||||
mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0],
|
||||
|
||||
@ -6,8 +6,7 @@ module fsgn (
|
||||
input logic XExpMaxE, // max possible exponent (all ones)
|
||||
input logic FmtE, // precision 1 = double 0 = single
|
||||
input logic [1:0] SgnOpCodeE, // operation control
|
||||
output logic [63:0] SgnResE, // result
|
||||
output logic SgnNVE // invalid flag
|
||||
output logic [63:0] SgnResE // result
|
||||
);
|
||||
|
||||
logic ResSgn;
|
||||
@ -27,12 +26,5 @@ module fsgn (
|
||||
// - if there are any unsused bits the most significant bits are filled with 1s
|
||||
assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]};
|
||||
|
||||
//If the exponent is all ones, then the value is either Inf or NaN,
|
||||
//both of which will produce a QNaN/SNaN value of some sort. This will
|
||||
//set the invalid flag high.
|
||||
|
||||
//the only flag that can occur during this operation is invalid
|
||||
//due to changing sign on already existing NaN
|
||||
assign SgnNVE = XExpMaxE & SgnResE[63];
|
||||
|
||||
endmodule
|
||||
|
||||
@ -75,7 +75,7 @@ module fsm_fpdiv (
|
||||
sel_muxr = 1'b0;
|
||||
next_state = S0;
|
||||
end
|
||||
else if (start==1'b1 && op_type==1'b0)
|
||||
else if (start==1'b1 & op_type==1'b0)
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
@ -89,8 +89,8 @@ module fsm_fpdiv (
|
||||
sel_muxb = 3'b001;
|
||||
sel_muxr = 1'b0;
|
||||
next_state = S1;
|
||||
end // if (start==1'b1 && op_type==1'b0)
|
||||
else if (start==1'b1 && op_type==1'b1)
|
||||
end // if (start==1'b1 & op_type==1'b0)
|
||||
else if (start==1'b1 & op_type==1'b1)
|
||||
begin
|
||||
done = 1'b0;
|
||||
divBusy = 1'b1;
|
||||
|
||||
@ -29,7 +29,7 @@ module hazard(
|
||||
// Detect hazards
|
||||
(* mark_debug = "true" *) input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
|
||||
(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
|
||||
(* mark_debug = "true" *) input logic LSUStall, ICacheStallF,
|
||||
(* mark_debug = "true" *) input logic LSUStall, IfuStallF,
|
||||
(* mark_debug = "true" *) input logic FPUStallD, FStallD,
|
||||
(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE,
|
||||
(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
|
||||
@ -55,11 +55,11 @@ module hazard(
|
||||
// A stage must stall if the next stage is stalled
|
||||
// If any stages are stalled, the first stage that isn't stalled must flush.
|
||||
|
||||
assign StallFCause = CSRWritePendingDEM && ~(TrapM | RetM | BPPredWrongE);
|
||||
assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
|
||||
assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
|
||||
assign StallECause = DivBusyE | FDivBusyE;
|
||||
assign StallMCause = 0;
|
||||
assign StallWCause = LSUStall | ICacheStallF;
|
||||
assign StallWCause = LSUStall | IfuStallF;
|
||||
|
||||
assign StallF = StallFCause | StallD;
|
||||
assign StallD = StallDCause | StallE;
|
||||
@ -67,10 +67,10 @@ module hazard(
|
||||
assign StallM = StallMCause | StallW;
|
||||
assign StallW = StallWCause;
|
||||
|
||||
assign FirstUnstalledD = (~StallD && StallF);
|
||||
assign FirstUnstalledE = (~StallE && StallD);
|
||||
assign FirstUnstalledM = (~StallM && StallE);
|
||||
assign FirstUnstalledW = (~StallW && StallM);
|
||||
assign FirstUnstalledD = ~StallD & StallF;
|
||||
assign FirstUnstalledE = ~StallE & StallD;
|
||||
assign FirstUnstalledM = ~StallM & StallE;
|
||||
assign FirstUnstalledW = ~StallW & StallM;
|
||||
|
||||
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
|
||||
assign FlushF = BPPredWrongE | InvalidateICacheM;
|
||||
|
||||
@ -134,16 +134,16 @@ module controller(
|
||||
ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0;; // amo
|
||||
end else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
7'b0110011: if (Funct7D == 7'b0000000 || Funct7D == 7'b0100000)
|
||||
7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000)
|
||||
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type
|
||||
else if (Funct7D == 7'b0000001 && `M_SUPPORTED)
|
||||
else if (Funct7D == 7'b0000001 & `M_SUPPORTED)
|
||||
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/Divide
|
||||
else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
|
||||
7'b0111011: if ((Funct7D == 7'b0000000 || Funct7D == 7'b0100000) && `XLEN == 64)
|
||||
7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64)
|
||||
ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
|
||||
else if (Funct7D == 7'b0000001 && `M_SUPPORTED && `XLEN == 64)
|
||||
else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64)
|
||||
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
|
||||
else
|
||||
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
|
||||
@ -168,7 +168,7 @@ module controller(
|
||||
// *** move Privileged, CSRwrite?? Or move controller out of IEU into datapath and handle all instructions
|
||||
|
||||
assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
|
||||
assign CSRWriteD = CSRReadD & !(CSRZeroSrcD && InstrD[13]); // Don't write if setting or clearing zeros
|
||||
assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
|
||||
|
||||
// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
|
||||
assign sltD = (Funct3D == 3'b010);
|
||||
@ -182,12 +182,12 @@ module controller(
|
||||
// Ordinary fence is presently a nop
|
||||
// FENCE.I flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
|
||||
generate
|
||||
if (`ZIFENCEI_SUPPORTED & `MEM_ICACHE) begin
|
||||
if (`ZIFENCEI_SUPPORTED & `MEM_ICACHE) begin:fencei
|
||||
logic FenceID;
|
||||
assign FenceID = FenceD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
|
||||
assign InvalidateICacheD = FenceID;
|
||||
assign FlushDCacheD = FenceID;
|
||||
end else begin
|
||||
end else begin:fencei
|
||||
assign InvalidateICacheD = 0;
|
||||
assign FlushDCacheD = 0;
|
||||
end
|
||||
|
||||
@ -128,7 +128,7 @@ module datapath (
|
||||
if (`F_SUPPORTED) begin:fpmux
|
||||
mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
|
||||
mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
|
||||
end else begin
|
||||
end else begin:fpmux
|
||||
assign ResultM = IEUResultM;
|
||||
assign WriteDataE = ForwardedSrcBE;
|
||||
end
|
||||
|
||||
@ -39,10 +39,10 @@ module decompress (
|
||||
|
||||
// if the system handles compressed instructions, decode appropriately
|
||||
generate
|
||||
if (!(`C_SUPPORTED)) begin // no compressed mode
|
||||
if (!(`C_SUPPORTED)) begin:decompress // no compressed mode
|
||||
assign InstrD = InstrRawD;
|
||||
assign IllegalCompInstrD = 0;
|
||||
end else begin // COMPRESSED mode supported
|
||||
end else begin : decompress // COMPRESSED mode supported
|
||||
assign instr16 = InstrRawD[15:0]; // instruction is alreay aligned
|
||||
assign op = instr16[1:0];
|
||||
assign rds1 = instr16[11:7];
|
||||
@ -124,7 +124,7 @@ module decompress (
|
||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
|
||||
else // if (instr16[6:5] == 2'b11)
|
||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
|
||||
else if (instr16[12:10] == 3'b111 && `XLEN > 32)
|
||||
else if (instr16[12:10] == 3'b111 & `XLEN > 32)
|
||||
if (instr16[6:5] == 2'b00)
|
||||
InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
|
||||
else if (instr16[6:5] == 2'b01)
|
||||
|
||||
@ -27,61 +27,54 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ifu (
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushF, FlushD, FlushE, FlushM, FlushW,
|
||||
// Fetch
|
||||
input logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
input logic ICacheBusAck,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
|
||||
output logic [`PA_BITS-1:0] ICacheBusAdr,
|
||||
output logic IfuBusFetch,
|
||||
output logic ICacheStallF,
|
||||
// Execute
|
||||
output logic [`XLEN-1:0] PCLinkE,
|
||||
input logic PCSrcE,
|
||||
input logic [`XLEN-1:0] IEUAdrE,
|
||||
output logic [`XLEN-1:0] PCE,
|
||||
output logic BPPredWrongE,
|
||||
// Mem
|
||||
input logic RetM, TrapM,
|
||||
input logic [`XLEN-1:0] PrivilegedNextPCM,
|
||||
input logic InvalidateICacheM,
|
||||
output logic [31:0] InstrD, InstrM,
|
||||
output logic [`XLEN-1:0] PCM,
|
||||
output logic [4:0] InstrClassM,
|
||||
output logic BPPredDirWrongM,
|
||||
output logic BTBPredPCWrongM,
|
||||
output logic RASPredPCWrongM,
|
||||
output logic BPPredClassNonCFIWrongM,
|
||||
// Writeback
|
||||
// output logic [`XLEN-1:0] PCLinkW,
|
||||
// Faults
|
||||
input logic IllegalBaseInstrFaultD,
|
||||
output logic ITLBInstrPageFaultF,
|
||||
output logic IllegalIEUInstrFaultD,
|
||||
output logic InstrMisalignedFaultM,
|
||||
output logic [`XLEN-1:0] InstrMisalignedAdrM,
|
||||
input logic ExceptionM, PendingInterruptM,
|
||||
|
||||
|
||||
|
||||
// mmu management
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic [`XLEN-1:0] PTE,
|
||||
input logic [1:0] PageType,
|
||||
input logic [`XLEN-1:0] SATP_REGW,
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
input logic [1:0] STATUS_MPP,
|
||||
input logic ITLBWriteF, ITLBFlushF,
|
||||
|
||||
output logic ITLBMissF,
|
||||
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushF, FlushD, FlushE, FlushM, FlushW,
|
||||
// Bus interface
|
||||
input logic [`XLEN-1:0] IfuBusHRDATA,
|
||||
input logic IfuBusAck,
|
||||
output logic [`PA_BITS-1:0] IfuBusAdr,
|
||||
output logic IfuBusRead,
|
||||
output logic IfuStallF,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
|
||||
// Execute
|
||||
output logic [`XLEN-1:0] PCLinkE,
|
||||
input logic PCSrcE,
|
||||
input logic [`XLEN-1:0] IEUAdrE,
|
||||
output logic [`XLEN-1:0] PCE,
|
||||
output logic BPPredWrongE,
|
||||
// Mem
|
||||
input logic RetM, TrapM,
|
||||
input logic [`XLEN-1:0] PrivilegedNextPCM,
|
||||
input logic InvalidateICacheM,
|
||||
output logic [31:0] InstrD, InstrM,
|
||||
output logic [`XLEN-1:0] PCM,
|
||||
// branch predictor
|
||||
output logic [4:0] InstrClassM,
|
||||
output logic BPPredDirWrongM,
|
||||
output logic BTBPredPCWrongM,
|
||||
output logic RASPredPCWrongM,
|
||||
output logic BPPredClassNonCFIWrongM,
|
||||
// Faults
|
||||
input logic IllegalBaseInstrFaultD,
|
||||
output logic ITLBInstrPageFaultF,
|
||||
output logic IllegalIEUInstrFaultD,
|
||||
output logic InstrMisalignedFaultM,
|
||||
output logic [`XLEN-1:0] InstrMisalignedAdrM,
|
||||
input logic ExceptionM, PendingInterruptM,
|
||||
// mmu management
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic [`XLEN-1:0] PTE,
|
||||
input logic [1:0] PageType,
|
||||
input logic [`XLEN-1:0] SATP_REGW,
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
input logic [1:0] STATUS_MPP,
|
||||
input logic ITLBWriteF, ITLBFlushF,
|
||||
output logic ITLBMissF,
|
||||
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
|
||||
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||
|
||||
output logic InstrAccessFaultF
|
||||
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||
output logic InstrAccessFaultF
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
|
||||
@ -91,44 +84,102 @@ module ifu (
|
||||
logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
|
||||
logic [`XLEN-3:0] PCPlusUpperF;
|
||||
logic CompressedF;
|
||||
logic [31:0] InstrRawD, FinalInstrRawF;
|
||||
logic [31:0] InstrRawD, FinalInstrRawF, InstrRawF;
|
||||
logic [31:0] InstrE;
|
||||
logic [`XLEN-1:0] PCD;
|
||||
|
||||
localparam [31:0] nop = 32'h00000013; // instruction for NOP
|
||||
localparam [31:0] nop = 32'h00000013; // instruction for NOP
|
||||
logic reset_q; // *** look at this later.
|
||||
|
||||
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
|
||||
|
||||
(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
|
||||
logic [`XLEN+1:0] PCFExt;
|
||||
logic [`XLEN-1:0] PCBPWrongInvalidate;
|
||||
logic BPPredWrongM;
|
||||
|
||||
|
||||
(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
|
||||
logic [`XLEN+1:0] PCFExt;
|
||||
|
||||
logic CacheableF;
|
||||
|
||||
|
||||
logic [11:0] PCNextFMux;
|
||||
logic [`XLEN-1:0] PCFMux;
|
||||
logic SelNextSpill;
|
||||
logic ICacheFetchLine;
|
||||
logic BusStall;
|
||||
logic ICacheStallF;
|
||||
logic IgnoreRequest;
|
||||
logic CPUBusy;
|
||||
logic [31:0] PostSpillInstrRawF;
|
||||
|
||||
|
||||
generate
|
||||
if (`XLEN==32) begin
|
||||
//assign PCPF = PCPFmmu[31:0];
|
||||
assign PCNextFPhys = {{(`PA_BITS-`XLEN){1'b0}}, PCNextF};
|
||||
end else begin
|
||||
//assign PCPF = {8'b0, PCPFmmu};
|
||||
assign PCNextFPhys = PCNextF[`PA_BITS-1:0];
|
||||
end
|
||||
endgenerate
|
||||
if(`C_SUPPORTED) begin : SpillSupport
|
||||
logic [`XLEN-1:0] PCFp2;
|
||||
logic Spill;
|
||||
logic SelSpill, SpillSave;
|
||||
logic [15:0] SpillDataBlock0;
|
||||
|
||||
assign PCFExt = {2'b00, PCF};
|
||||
// this exists only if there are compressed instructions.
|
||||
assign PCFp2 = PCF + `XLEN'b10;
|
||||
|
||||
assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
|
||||
assign PCFMux = SelSpill ? PCFp2 : PCF;
|
||||
|
||||
assign Spill = &PCF[$clog2(`ICACHE_BLOCKLENINBITS/32)+1:1];
|
||||
|
||||
typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_SPILL_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
always_comb begin
|
||||
case(CurrState)
|
||||
STATE_SPILL_READY: if (Spill & ~(ICacheStallF | BusStall)) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
STATE_SPILL_SPILL: if(ICacheStallF | BusStall | StallF) NextState = STATE_SPILL_SPILL;
|
||||
else NextState = STATE_SPILL_READY;
|
||||
default: NextState = STATE_SPILL_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign SelSpill = CurrState == STATE_SPILL_SPILL;
|
||||
assign SelNextSpill = (CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall))) |
|
||||
(CurrState == STATE_SPILL_SPILL & (ICacheStallF | BusStall));
|
||||
assign SpillSave = CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall));
|
||||
|
||||
|
||||
flopenr #(16) SpillInstrReg(.clk(clk),
|
||||
.en(SpillSave),
|
||||
.reset(reset),
|
||||
.d(InstrRawF[15:0]),
|
||||
.q(SpillDataBlock0));
|
||||
|
||||
assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataBlock0} : InstrRawF;
|
||||
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
|
||||
|
||||
// end of spill support
|
||||
end else begin : NoSpillSupport // block: SpillSupport
|
||||
assign PCNextFMux = PCNextF[11:0];
|
||||
assign PCFMux = PCF;
|
||||
assign SelNextSpill = 0;
|
||||
assign PostSpillInstrRawF = InstrRawF;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
assign PCFExt = {2'b00, PCFMux};
|
||||
//
|
||||
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
|
||||
immu(.PAdr(PCFExt[`PA_BITS-1:0]),
|
||||
.VAdr(PCF),
|
||||
.VAdr(PCFMux),
|
||||
.Size(2'b10),
|
||||
.PTE(PTE),
|
||||
.PageTypeWriteVal(PageType),
|
||||
.TLBWrite(ITLBWriteF),
|
||||
.TLBFlush(ITLBFlushF),
|
||||
.PhysicalAddress(PCPFmmu),
|
||||
.PhysicalAddress(PCPF),
|
||||
.TLBMiss(ITLBMissF),
|
||||
.TLBPageFault(ITLBInstrPageFaultF),
|
||||
.ExecuteAccessF(1'b1), // ***dh -- this should eventually change to only true if an instruction fetch is occurring
|
||||
@ -156,6 +207,7 @@ module ifu (
|
||||
logic SelBPPredF;
|
||||
logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
|
||||
logic [4:0] InstrClassD, InstrClassE;
|
||||
|
||||
|
||||
|
||||
// *** put memory interface on here, InstrF becomes output
|
||||
@ -167,15 +219,84 @@ module ifu (
|
||||
// 1. ram // controlled by `MEM_IROM
|
||||
// 2. cache // `MEM_ICACHE
|
||||
// 3. wire pass-through
|
||||
icache icache(.clk, .reset, .CPUBusy(StallF), .ExceptionM, .PendingInterruptM, .IfuBusHRDATA, .ICacheBusAck,
|
||||
.ICacheBusAdr, .IfuBusFetch, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
|
||||
.CacheableF,
|
||||
.PCNextF(PCNextFPhys),
|
||||
.PCPF(PCPFmmu),
|
||||
.PCF,
|
||||
.InvalidateICacheM);
|
||||
|
||||
localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS/`XLEN : 1;
|
||||
localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1;
|
||||
localparam integer BLOCKLEN = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS : `XLEN;
|
||||
localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0;
|
||||
|
||||
localparam integer BLOCKBYTELEN = BLOCKLEN/8;
|
||||
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
|
||||
|
||||
logic [LOGWPL-1:0] WordCount;
|
||||
logic [BLOCKLEN-1:0] ICacheMemWriteData;
|
||||
logic ICacheBusAck;
|
||||
logic [`PA_BITS-1:0] LocalIfuBusAdr;
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic SelUncachedAdr;
|
||||
|
||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
|
||||
|
||||
|
||||
|
||||
generate
|
||||
if(`MEM_ICACHE) begin : icache
|
||||
icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
|
||||
.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
|
||||
.ICacheFetchLine,
|
||||
.CacheableF,
|
||||
.PCNextF(PCNextFMux),
|
||||
.PCPF(PCPF),
|
||||
.PCF(PCFMux),
|
||||
.InvalidateICacheM);
|
||||
|
||||
end else begin : passthrough
|
||||
assign ICacheFetchLine = 0;
|
||||
assign ICacheBusAdr = 0;
|
||||
//assign CompressedF = 0; //?
|
||||
assign ICacheStallF = 0;
|
||||
assign FinalInstrRawF = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// select between dcache and direct from the BUS. Always selected if no dcache.
|
||||
// handled in the busfsm.
|
||||
mux2 #(32) UnCachedInstrMux(.d0(FinalInstrRawF),
|
||||
.d1(ICacheMemWriteData[31:0]),
|
||||
.s(SelUncachedAdr),
|
||||
.y(InstrRawF));
|
||||
|
||||
// always present
|
||||
genvar index;
|
||||
generate
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||
flopen #(`XLEN) fb(.clk(clk),
|
||||
.en(IfuBusAck & IfuBusRead & (index == WordCount)),
|
||||
.d(IfuBusHRDATA),
|
||||
.q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign LocalIfuBusAdr = SelUncachedAdr ? PCPF : ICacheBusAdr;
|
||||
assign IfuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIfuBusAdr;
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL, `MEM_ICACHE)
|
||||
busfsm(.clk, .reset, .IgnoreRequest,
|
||||
.LsuRWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0),
|
||||
.LsuBusAck(IfuBusAck),
|
||||
.CPUBusy, .CacheableM(CacheableF),
|
||||
.BusStall, .LsuBusWrite(), .LsuBusRead(IfuBusRead), .DCacheBusAck(ICacheBusAck),
|
||||
.BusCommittedM(), .SelUncachedAdr(SelUncachedAdr), .WordCount);
|
||||
|
||||
assign IfuStallF = ICacheStallF | BusStall | SelNextSpill;
|
||||
assign CPUBusy = StallF & ~SelNextSpill;
|
||||
|
||||
//assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
|
||||
// this is a difference with the dcache.
|
||||
// uses interlock fsm.
|
||||
assign IgnoreRequest = ITLBMissF;
|
||||
|
||||
|
||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
|
||||
|
||||
|
||||
assign PrivilegedChangePCM = RetM | TrapM;
|
||||
@ -232,23 +353,12 @@ module ifu (
|
||||
// I am making the port connection explicit for now as I want to see them and they will be changing.
|
||||
|
||||
bpred bpred(.clk, .reset,
|
||||
.StallF, .StallD, .StallE,
|
||||
.FlushF, .FlushD, .FlushE,
|
||||
|
||||
.PCNextF(PCNextF),
|
||||
.BPPredPCF(BPPredPCF),
|
||||
.SelBPPredF(SelBPPredF),
|
||||
.PCE(PCE),
|
||||
.PCSrcE(PCSrcE),
|
||||
.IEUAdrE(IEUAdrE),
|
||||
.PCD(PCD),
|
||||
.PCLinkE(PCLinkE),
|
||||
.InstrClassE(InstrClassE),
|
||||
.BPPredWrongE(BPPredWrongE),
|
||||
.BPPredDirWrongE(BPPredDirWrongE),
|
||||
.BTBPredPCWrongE(BTBPredPCWrongE),
|
||||
.RASPredPCWrongE(RASPredPCWrongE),
|
||||
.BPPredClassNonCFIWrongE(BPPredClassNonCFIWrongE));
|
||||
.StallF, .StallD, .StallE,
|
||||
.FlushF, .FlushD, .FlushE,
|
||||
.PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
|
||||
.PCD, .PCLinkE, .InstrClassE, .BPPredWrongE, .BPPredDirWrongE,
|
||||
.BTBPredPCWrongE, .RASPredPCWrongE, .BPPredClassNonCFIWrongE);
|
||||
|
||||
end else begin : bpred
|
||||
assign BPPredPCF = {`XLEN{1'b0}};
|
||||
assign SelBPPredF = 1'b0;
|
||||
@ -284,20 +394,18 @@ module ifu (
|
||||
|
||||
// the branch predictor needs a compact decoding of the instruction class.
|
||||
// *** consider adding in the alternate return address x5 for returns.
|
||||
assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 && (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
|
||||
assign InstrClassD[3] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
|
||||
assign InstrClassD[2] = InstrD[6:0] == 7'h67 && (InstrD[19:15] & 5'h1B) != 5'h01 && (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
|
||||
assign InstrClassD[1] = InstrD[6:0] == 7'h6F && (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
|
||||
assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
|
||||
assign InstrClassD[3] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
|
||||
assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
|
||||
assign InstrClassD[1] = InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
|
||||
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
|
||||
|
||||
// Misaligned PC logic
|
||||
|
||||
generate
|
||||
if (`C_SUPPORTED) // C supports compressed instructions on halfword boundaries
|
||||
assign misaligned = PCNextF[0];
|
||||
else // instructions must be on word boundaries
|
||||
assign misaligned = |PCNextF[1:0];
|
||||
endgenerate
|
||||
// instruction address misalignment is generated by the target of control flow instructions, not
|
||||
// the fetch itself.
|
||||
assign misaligned = PCNextF[0] | (PCNextF[1] & ~`C_SUPPORTED);
|
||||
// do we really need to have check if the instruction is control flow? Yes
|
||||
// Branches are updated in the execution stage but traps are updated in the memory stage.
|
||||
|
||||
// pipeline misaligned faults to M stage
|
||||
assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned
|
||||
|
||||
@ -71,7 +71,7 @@ module localHistoryPredictor
|
||||
|
||||
flopenr #(k) LocalHistoryRegister(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(UpdateEN && (index == UpdatePCIndex)),
|
||||
.en(UpdateEN & (index == UpdatePCIndex)),
|
||||
.d(LHRFNext),
|
||||
.q(LHRNextF[index]));
|
||||
end
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
|
||||
|
||||
module busfsm #(parameter integer WordCountThreshold,
|
||||
parameter integer LOGWPL)
|
||||
parameter integer LOGWPL, parameter logic CacheEnabled )
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
|
||||
@ -55,7 +55,8 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
logic CntReset;
|
||||
logic WordCountFlag;
|
||||
logic [LOGWPL-1:0] NextWordCount;
|
||||
|
||||
logic UnCachedAccess;
|
||||
|
||||
|
||||
typedef enum {STATE_BUS_READY,
|
||||
STATE_BUS_FETCH,
|
||||
@ -81,6 +82,8 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
|
||||
assign CntEn = PreCntEn & LsuBusAck;
|
||||
|
||||
assign UnCachedAccess = ~CacheEnabled | ~CacheableM;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) BusCurrState <= #1 STATE_BUS_READY;
|
||||
else BusCurrState <= #1 BusNextState;
|
||||
@ -88,8 +91,8 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
always_comb begin
|
||||
case(BusCurrState)
|
||||
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
|
||||
else if(LsuRWM[0] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||
else if(LsuRWM[1] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_READ;
|
||||
else if(LsuRWM[0] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||
else if(LsuRWM[1] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_READ;
|
||||
else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH;
|
||||
else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE;
|
||||
else BusNextState = STATE_BUS_READY;
|
||||
@ -113,27 +116,27 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
|
||||
|
||||
assign CntReset = BusCurrState == STATE_BUS_READY;
|
||||
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) |
|
||||
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_READ) |
|
||||
(BusCurrState == STATE_BUS_FETCH) |
|
||||
(BusCurrState == STATE_BUS_WRITE);
|
||||
assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE;
|
||||
assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (LsuRWM[0])) |
|
||||
assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (LsuRWM[0])) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_WRITE);
|
||||
assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE);
|
||||
|
||||
assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) |
|
||||
assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (|LsuRWM[1])) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_READ);
|
||||
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH);
|
||||
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
|
||||
|
||||
assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
|
||||
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);
|
||||
assign BusCommittedM = BusCurrState != STATE_BUS_READY;
|
||||
assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & ~CacheableM)) |
|
||||
assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & UnCachedAccess)) |
|
||||
(BusCurrState == STATE_BUS_UNCACHED_READ |
|
||||
BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
|
||||
BusCurrState == STATE_BUS_UNCACHED_WRITE |
|
||||
BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) |
|
||||
~`MEM_DCACHE; // if no dcache always select uncachedadr.
|
||||
~CacheEnabled; // if no dcache always select uncachedadr.
|
||||
endmodule
|
||||
|
||||
@ -43,14 +43,14 @@ module lrsc
|
||||
logic lrM, scM, WriteAdrMatchM;
|
||||
logic SquashSCM;
|
||||
|
||||
assign lrM = MemReadM && LsuAtomicM[0];
|
||||
assign scM = PreLsuRWM[0] && LsuAtomicM[0];
|
||||
assign WriteAdrMatchM = PreLsuRWM[0] && (LsuPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
|
||||
assign SquashSCM = scM && ~WriteAdrMatchM;
|
||||
assign lrM = MemReadM & LsuAtomicM[0];
|
||||
assign scM = PreLsuRWM[0] & LsuAtomicM[0];
|
||||
assign WriteAdrMatchM = PreLsuRWM[0] & (LsuPAdrM[`PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
|
||||
assign SquashSCM = scM & ~WriteAdrMatchM;
|
||||
assign LsuRWM = SquashSCM ? 2'b00 : PreLsuRWM;
|
||||
always_comb begin // ReservationValidM (next value of valid reservation)
|
||||
if (lrM) ReservationValidM = 1; // set valid on load reserve
|
||||
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
|
||||
else if (scM | WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
|
||||
else ReservationValidM = ReservationValidW; // otherwise don't change valid
|
||||
end
|
||||
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, LsuPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
|
||||
|
||||
@ -121,73 +121,73 @@ module lsu
|
||||
assign IEUAdrExtM = {2'b00, IEUAdrM};
|
||||
|
||||
generate
|
||||
if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
|
||||
logic AnyCPUReqM;
|
||||
logic [`PA_BITS-1:0] HPTWAdr;
|
||||
logic HPTWRead;
|
||||
logic [2:0] HPTWSize;
|
||||
logic SelReplayCPURequest;
|
||||
if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
|
||||
logic AnyCPUReqM;
|
||||
logic [`PA_BITS-1:0] HPTWAdr;
|
||||
logic HPTWRead;
|
||||
logic [2:0] HPTWSize;
|
||||
logic SelReplayCPURequest;
|
||||
|
||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||
|
||||
interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
|
||||
.DTLBMissM, .DTLBWriteM, .ExceptionM, .PendingInterruptM, .DCacheStall,
|
||||
.InterlockStall, .SelReplayCPURequest, .SelHPTW,
|
||||
.IgnoreRequest);
|
||||
|
||||
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
|
||||
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
|
||||
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
|
||||
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
|
||||
.HPTWReadPTE(ReadDataM),
|
||||
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
|
||||
interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF,
|
||||
.DTLBMissM, .DTLBWriteM, .ExceptionM, .PendingInterruptM, .DCacheStall,
|
||||
.InterlockStall, .SelReplayCPURequest, .SelHPTW,
|
||||
.IgnoreRequest);
|
||||
|
||||
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
|
||||
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
|
||||
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
|
||||
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
|
||||
.HPTWReadPTE(ReadDataM),
|
||||
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
|
||||
|
||||
// arbiter between IEU and hptw
|
||||
|
||||
// multiplex the outputs to LSU
|
||||
mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLsuRWM);
|
||||
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M);
|
||||
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM);
|
||||
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLsuAdrE);
|
||||
mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLsuPAdrM);
|
||||
// arbiter between IEU and hptw
|
||||
|
||||
// multiplex the outputs to LSU
|
||||
mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLsuRWM);
|
||||
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M);
|
||||
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM);
|
||||
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLsuAdrE);
|
||||
mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLsuPAdrM);
|
||||
|
||||
// always block interrupts when using the hardware page table walker.
|
||||
assign CPUBusy = StallW & ~SelHPTW;
|
||||
|
||||
// It is not possible to pipeline hptw as the following load will depend on the previous load's
|
||||
// data. Therefore we don't need a pipeline register
|
||||
//flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
|
||||
// always block interrupts when using the hardware page table walker.
|
||||
assign CPUBusy = StallW & ~SelHPTW;
|
||||
|
||||
// It is not possible to pipeline hptw as the following load will depend on the previous load's
|
||||
// data. Therefore we don't need a pipeline register
|
||||
//flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
|
||||
|
||||
// Specify which type of page fault is occurring
|
||||
assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLsuRWM[1];
|
||||
assign DTLBStorePageFaultM = DTLBPageFaultM & PreLsuRWM[0];
|
||||
// Specify which type of page fault is occurring
|
||||
assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLsuRWM[1];
|
||||
assign DTLBStorePageFaultM = DTLBPageFaultM & PreLsuRWM[0];
|
||||
|
||||
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
||||
assign LsuAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : PreLsuAdrE;
|
||||
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
||||
assign LsuAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : PreLsuAdrE;
|
||||
|
||||
end // if (`MEM_VIRTMEM)
|
||||
else begin
|
||||
assign InterlockStall = 1'b0;
|
||||
|
||||
assign LsuAdrE = PreLsuAdrE;
|
||||
assign SelHPTW = 1'b0;
|
||||
assign IgnoreRequest = 1'b0;
|
||||
end // if (`MEM_VIRTMEM)
|
||||
else begin
|
||||
assign InterlockStall = 1'b0;
|
||||
|
||||
assign LsuAdrE = PreLsuAdrE;
|
||||
assign SelHPTW = 1'b0;
|
||||
assign IgnoreRequest = 1'b0;
|
||||
|
||||
assign PTE = '0;
|
||||
assign PageType = '0;
|
||||
assign DTLBWriteM = 1'b0;
|
||||
assign ITLBWriteF = 1'b0;
|
||||
|
||||
assign PreLsuRWM = MemRWM;
|
||||
assign LsuFunct3M = Funct3M;
|
||||
assign LsuAtomicM = AtomicM;
|
||||
assign PreLsuAdrE = IEUAdrE[11:0];
|
||||
assign PreLsuPAdrM = IEUAdrExtM;
|
||||
assign CPUBusy = StallW;
|
||||
|
||||
assign DTLBLoadPageFaultM = 1'b0;
|
||||
assign DTLBStorePageFaultM = 1'b0;
|
||||
end
|
||||
assign PTE = '0;
|
||||
assign PageType = '0;
|
||||
assign DTLBWriteM = 1'b0;
|
||||
assign ITLBWriteF = 1'b0;
|
||||
|
||||
assign PreLsuRWM = MemRWM;
|
||||
assign LsuFunct3M = Funct3M;
|
||||
assign LsuAtomicM = AtomicM;
|
||||
assign PreLsuAdrE = IEUAdrE[11:0];
|
||||
assign PreLsuPAdrM = IEUAdrExtM;
|
||||
assign CPUBusy = StallW;
|
||||
|
||||
assign DTLBLoadPageFaultM = 1'b0;
|
||||
assign DTLBStorePageFaultM = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// **** look into this confusing signal.
|
||||
@ -201,54 +201,54 @@ module lsu
|
||||
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
|
||||
|
||||
generate
|
||||
if(`ZICSR_SUPPORTED == 1) begin : dmmu
|
||||
logic DataMisalignedM;
|
||||
if(`ZICSR_SUPPORTED == 1) begin : dmmu
|
||||
logic DataMisalignedM;
|
||||
|
||||
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
.PrivilegeModeW, .DisableTranslation(SelHPTW),
|
||||
.PAdr(PreLsuPAdrM),
|
||||
.VAdr(IEUAdrM),
|
||||
.Size(LsuFunct3M[1:0]),
|
||||
.PTE,
|
||||
.PageTypeWriteVal(PageType),
|
||||
.TLBWrite(DTLBWriteM),
|
||||
.TLBFlush(DTLBFlushM),
|
||||
.PhysicalAddress(LsuPAdrM),
|
||||
.TLBMiss(DTLBMissM),
|
||||
.Cacheable(CacheableM),
|
||||
.Idempotent(), .AtomicAllowed(),
|
||||
.TLBPageFault(DTLBPageFaultM),
|
||||
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
|
||||
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), /// atomicaccessm is probably a bug
|
||||
.WriteAccessM(PreLsuRWM[0]), .ReadAccessM(PreLsuRWM[1]),
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
|
||||
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
|
||||
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
.PrivilegeModeW, .DisableTranslation(SelHPTW),
|
||||
.PAdr(PreLsuPAdrM),
|
||||
.VAdr(IEUAdrM),
|
||||
.Size(LsuFunct3M[1:0]),
|
||||
.PTE,
|
||||
.PageTypeWriteVal(PageType),
|
||||
.TLBWrite(DTLBWriteM),
|
||||
.TLBFlush(DTLBFlushM),
|
||||
.PhysicalAddress(LsuPAdrM),
|
||||
.TLBMiss(DTLBMissM),
|
||||
.Cacheable(CacheableM),
|
||||
.Idempotent(), .AtomicAllowed(),
|
||||
.TLBPageFault(DTLBPageFaultM),
|
||||
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
|
||||
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), /// atomicaccessm is probably a bug
|
||||
.WriteAccessM(PreLsuRWM[0]), .ReadAccessM(PreLsuRWM[1]),
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
|
||||
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
|
||||
|
||||
// Determine if an Unaligned access is taking place
|
||||
// hptw guarantees alignment, only check inputs from IEU.
|
||||
always_comb
|
||||
case(Funct3M[1:0])
|
||||
2'b00: DataMisalignedM = 0; // lb, sb, lbu
|
||||
2'b01: DataMisalignedM = IEUAdrM[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
|
||||
endcase
|
||||
// Determine if an Unaligned access is taking place
|
||||
// hptw guarantees alignment, only check inputs from IEU.
|
||||
always_comb
|
||||
case(Funct3M[1:0])
|
||||
2'b00: DataMisalignedM = 0; // lb, sb, lbu
|
||||
2'b01: DataMisalignedM = IEUAdrM[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
|
||||
endcase
|
||||
|
||||
// If the CPU's (not HPTW's) request is a page fault.
|
||||
assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
|
||||
assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
|
||||
|
||||
end else begin
|
||||
assign LsuPAdrM = PreLsuPAdrM;
|
||||
assign DTLBMissM = 0;
|
||||
assign CacheableM = 1;
|
||||
assign DTLBPageFaultM = 0;
|
||||
assign LoadAccessFaultM = 0;
|
||||
assign StoreAccessFaultM = 0;
|
||||
assign LoadMisalignedFaultM = 0;
|
||||
assign StoreMisalignedFaultM = 0;
|
||||
end
|
||||
// If the CPU's (not HPTW's) request is a page fault.
|
||||
assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
|
||||
assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
|
||||
|
||||
end else begin
|
||||
assign LsuPAdrM = PreLsuPAdrM;
|
||||
assign DTLBMissM = 0;
|
||||
assign CacheableM = 1;
|
||||
assign DTLBPageFaultM = 0;
|
||||
assign LoadAccessFaultM = 0;
|
||||
assign StoreAccessFaultM = 0;
|
||||
assign LoadMisalignedFaultM = 0;
|
||||
assign StoreMisalignedFaultM = 0;
|
||||
end
|
||||
endgenerate
|
||||
assign LSUStall = DCacheStall | InterlockStall | BusStall;
|
||||
|
||||
@ -257,25 +257,24 @@ module lsu
|
||||
// Move generate from lrsc to outside this module.
|
||||
// use PreLsu as prefix for lrsc
|
||||
generate
|
||||
if (`A_SUPPORTED) begin
|
||||
assign MemReadM = PreLsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
|
||||
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLsuRWM, .LsuAtomicM, .LsuPAdrM,
|
||||
.SquashSCW, .LsuRWM);
|
||||
end else begin
|
||||
assign SquashSCW = 0;
|
||||
assign LsuRWM = PreLsuRWM;
|
||||
end
|
||||
if (`A_SUPPORTED) begin:lrsc
|
||||
assign MemReadM = PreLsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
|
||||
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLsuRWM, .LsuAtomicM, .LsuPAdrM,
|
||||
.SquashSCW, .LsuRWM);
|
||||
end else begin:lrsc
|
||||
assign SquashSCW = 0;
|
||||
assign LsuRWM = PreLsuRWM;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
// conditional
|
||||
// 1. ram // controlled by `MEM_DTIM
|
||||
// 2. cache `MEM_DCACHE
|
||||
// 3. wire pass-through
|
||||
|
||||
localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : `XLEN/8;
|
||||
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : 1;
|
||||
localparam integer LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1;
|
||||
localparam integer BLOCKLEN = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS : `XLEN;
|
||||
localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0;
|
||||
|
||||
@ -306,25 +305,25 @@ module lsu
|
||||
logic SelUncachedAdr;
|
||||
|
||||
generate
|
||||
if(`MEM_DCACHE) begin : dcache
|
||||
dcache dcache(.clk, .reset, .CPUBusy,
|
||||
.LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM,
|
||||
.FinalWriteDataM, .ReadDataWordM, .DCacheStall,
|
||||
.DCacheMiss, .DCacheAccess,
|
||||
.IgnoreRequest, .CacheableM, .DCacheCommittedM,
|
||||
.DCacheBusAdr, .ReadDataBlockSetsM, .DCacheMemWriteData,
|
||||
.DCacheFetchLine, .DCacheWriteLine,.DCacheBusAck);
|
||||
end else begin : passthrough
|
||||
assign ReadDataWordM = 0;
|
||||
assign DCacheStall = 0;
|
||||
assign DCacheMiss = 1;
|
||||
assign DCacheAccess = CacheableM;
|
||||
assign DCacheCommittedM = 0;
|
||||
assign DCacheWriteLine = 0;
|
||||
assign DCacheFetchLine = 0;
|
||||
assign DCacheBusAdr = 0;
|
||||
assign ReadDataBlockSetsM[0] = 0;
|
||||
end
|
||||
if(`MEM_DCACHE) begin : dcache
|
||||
dcache dcache(.clk, .reset, .CPUBusy,
|
||||
.LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM,
|
||||
.FinalWriteDataM, .ReadDataWordM, .DCacheStall,
|
||||
.DCacheMiss, .DCacheAccess,
|
||||
.IgnoreRequest, .CacheableM, .DCacheCommittedM,
|
||||
.DCacheBusAdr, .ReadDataBlockSetsM, .DCacheMemWriteData,
|
||||
.DCacheFetchLine, .DCacheWriteLine,.DCacheBusAck);
|
||||
end else begin : passthrough
|
||||
assign ReadDataWordM = 0;
|
||||
assign DCacheStall = 0;
|
||||
assign DCacheMiss = 1;
|
||||
assign DCacheAccess = CacheableM;
|
||||
assign DCacheCommittedM = 0;
|
||||
assign DCacheWriteLine = 0;
|
||||
assign DCacheFetchLine = 0;
|
||||
assign DCacheBusAdr = 0;
|
||||
assign ReadDataBlockSetsM[0] = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
@ -385,7 +384,7 @@ module lsu
|
||||
else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011;
|
||||
endgenerate;
|
||||
|
||||
busfsm #(WordCountThreshold, LOGWPL)
|
||||
busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
|
||||
busfsm(.clk, .reset, .IgnoreRequest, .LsuRWM, .DCacheFetchLine, .DCacheWriteLine,
|
||||
.LsuBusAck, .CPUBusy, .CacheableM, .BusStall, .LsuBusWrite, .LsuBusRead,
|
||||
.DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);
|
||||
|
||||
@ -39,7 +39,7 @@ module subwordread
|
||||
// Funct3M[1:0] is the size of the memory access.
|
||||
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
if (`XLEN == 64) begin:swrmux
|
||||
// ByteMe mux
|
||||
always_comb
|
||||
case(LsuPAdrM[2:0])
|
||||
@ -82,7 +82,7 @@ module subwordread
|
||||
3'b110: ReadDataM = {32'b0, WordM[31:0]}; // lwu
|
||||
default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
|
||||
endcase
|
||||
end else begin // 32-bit
|
||||
end else begin :swrmux // 32-bit
|
||||
// byte mux
|
||||
always_comb
|
||||
case(LsuPAdrM[1:0])
|
||||
|
||||
@ -46,7 +46,7 @@ module adrdec (
|
||||
// determine if legal size of access is being made (byte, halfword, word, doubleword)
|
||||
assign SizeValid = SizeMask[Size];
|
||||
|
||||
assign Sel = Match && Supported && AccessValid && SizeValid;
|
||||
assign Sel = Match & Supported & AccessValid & SizeValid;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -48,162 +48,154 @@ module hptw
|
||||
output logic [2:0] HPTWSize // 32 or 64 bit access.
|
||||
);
|
||||
|
||||
typedef enum {L0_ADR, L0_RD,
|
||||
L1_ADR, L1_RD,
|
||||
L2_ADR, L2_RD,
|
||||
L3_ADR, L3_RD,
|
||||
LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors
|
||||
typedef enum {L0_ADR, L0_RD,
|
||||
L1_ADR, L1_RD,
|
||||
L2_ADR, L2_RD,
|
||||
L3_ADR, L3_RD,
|
||||
LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors
|
||||
|
||||
generate
|
||||
if (`MEM_VIRTMEM) begin
|
||||
logic DTLBWalk; // register TLBs translation miss requests
|
||||
logic [`PPN_BITS-1:0] BasePageTablePPN;
|
||||
logic [`PPN_BITS-1:0] CurrentPPN;
|
||||
logic MemWrite;
|
||||
logic Executable, Writable, Readable, Valid;
|
||||
logic Misaligned, MegapageMisaligned;
|
||||
logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
|
||||
logic StartWalk;
|
||||
logic TLBMiss;
|
||||
logic PRegEn;
|
||||
logic [1:0] NextPageType;
|
||||
logic [`SVMODE_BITS-1:0] SvMode;
|
||||
logic [`XLEN-1:0] TranslationVAdr;
|
||||
|
||||
(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
|
||||
logic DTLBWalk; // register TLBs translation miss requests
|
||||
logic [`PPN_BITS-1:0] BasePageTablePPN;
|
||||
logic [`PPN_BITS-1:0] CurrentPPN;
|
||||
logic MemWrite;
|
||||
logic Executable, Writable, Readable, Valid;
|
||||
logic Misaligned, MegapageMisaligned;
|
||||
logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
|
||||
logic StartWalk;
|
||||
logic TLBMiss;
|
||||
logic PRegEn;
|
||||
logic [1:0] NextPageType;
|
||||
logic [`SVMODE_BITS-1:0] SvMode;
|
||||
logic [`XLEN-1:0] TranslationVAdr;
|
||||
|
||||
// Extract bits from CSRs and inputs
|
||||
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
|
||||
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
|
||||
assign MemWrite = MemRWM[0];
|
||||
assign TLBMiss = (DTLBMissM | ITLBMissF);
|
||||
(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
|
||||
|
||||
// Determine which address to translate
|
||||
assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
|
||||
assign CurrentPPN = PTE[`PPN_BITS+9:10];
|
||||
// Extract bits from CSRs and inputs
|
||||
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
|
||||
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
|
||||
assign MemWrite = MemRWM[0];
|
||||
assign TLBMiss = (DTLBMissM | ITLBMissF);
|
||||
|
||||
// State flops
|
||||
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
|
||||
assign PRegEn = HPTWRead & ~DCacheStall;
|
||||
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
|
||||
|
||||
// Assign PTE descriptors common across all XLEN values
|
||||
// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
|
||||
assign {Executable, Writable, Readable, Valid} = PTE[3:0];
|
||||
assign LeafPTE = Executable | Writable | Readable;
|
||||
assign ValidPTE = Valid && ~(Writable && ~Readable);
|
||||
assign ValidLeafPTE = ValidPTE & LeafPTE;
|
||||
assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
|
||||
|
||||
// Enable and select signals based on states
|
||||
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
|
||||
assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
|
||||
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
||||
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
||||
// Determine which address to translate
|
||||
assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
|
||||
assign CurrentPPN = PTE[`PPN_BITS+9:10];
|
||||
|
||||
// FSM to track PageType based on the levels of the page table traversed
|
||||
flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
|
||||
always_comb
|
||||
case (WalkerState)
|
||||
L3_RD: NextPageType = 2'b11; // terapage
|
||||
L2_RD: NextPageType = 2'b10; // gigapage
|
||||
L1_RD: NextPageType = 2'b01; // megapage
|
||||
L0_RD: NextPageType = 2'b00; // kilopage
|
||||
default: NextPageType = PageType;
|
||||
// State flops
|
||||
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
|
||||
assign PRegEn = HPTWRead & ~DCacheStall;
|
||||
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
|
||||
|
||||
// Assign PTE descriptors common across all XLEN values
|
||||
// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
|
||||
assign {Executable, Writable, Readable, Valid} = PTE[3:0];
|
||||
assign LeafPTE = Executable | Writable | Readable;
|
||||
assign ValidPTE = Valid & ~(Writable & ~Readable);
|
||||
assign ValidLeafPTE = ValidPTE & LeafPTE;
|
||||
assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
|
||||
|
||||
// Enable and select signals based on states
|
||||
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
|
||||
assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
|
||||
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
||||
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
||||
|
||||
// FSM to track PageType based on the levels of the page table traversed
|
||||
flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
|
||||
always_comb
|
||||
case (WalkerState)
|
||||
L3_RD: NextPageType = 2'b11; // terapage
|
||||
L2_RD: NextPageType = 2'b10; // gigapage
|
||||
L1_RD: NextPageType = 2'b01; // megapage
|
||||
L0_RD: NextPageType = 2'b00; // kilopage
|
||||
default: NextPageType = PageType;
|
||||
endcase
|
||||
|
||||
// HPTWAdr muxing
|
||||
if (`XLEN==32) begin // RV32
|
||||
logic [9:0] VPN;
|
||||
logic [`PPN_BITS-1:0] PPN;
|
||||
assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
|
||||
assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN;
|
||||
assign HPTWAdr = {PPN, VPN, 2'b00};
|
||||
assign HPTWSize = 3'b010;
|
||||
end else begin // RV64
|
||||
logic [8:0] VPN;
|
||||
logic [`PPN_BITS-1:0] PPN;
|
||||
always_comb
|
||||
case (WalkerState) // select VPN field based on HPTW state
|
||||
L3_ADR, L3_RD: VPN = TranslationVAdr[47:39];
|
||||
L2_ADR, L2_RD: VPN = TranslationVAdr[38:30];
|
||||
L1_ADR, L1_RD: VPN = TranslationVAdr[29:21];
|
||||
default: VPN = TranslationVAdr[20:12];
|
||||
endcase
|
||||
assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) |
|
||||
(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
|
||||
assign HPTWAdr = {PPN, VPN, 3'b000};
|
||||
assign HPTWSize = 3'b011;
|
||||
end
|
||||
|
||||
// HPTWAdr muxing
|
||||
if (`XLEN==32) begin // RV32
|
||||
logic [9:0] VPN;
|
||||
logic [`PPN_BITS-1:0] PPN;
|
||||
assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
|
||||
assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN;
|
||||
assign HPTWAdr = {PPN, VPN, 2'b00};
|
||||
assign HPTWSize = 3'b010;
|
||||
end else begin // RV64
|
||||
logic [8:0] VPN;
|
||||
logic [`PPN_BITS-1:0] PPN;
|
||||
always_comb
|
||||
case (WalkerState) // select VPN field based on HPTW state
|
||||
L3_ADR, L3_RD: VPN = TranslationVAdr[47:39];
|
||||
L2_ADR, L2_RD: VPN = TranslationVAdr[38:30];
|
||||
L1_ADR, L1_RD: VPN = TranslationVAdr[29:21];
|
||||
default: VPN = TranslationVAdr[20:12];
|
||||
endcase
|
||||
assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) |
|
||||
(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
|
||||
assign HPTWAdr = {PPN, VPN, 3'b000};
|
||||
assign HPTWSize = 3'b011;
|
||||
end
|
||||
// Initial state and misalignment for RV32/64
|
||||
if (`XLEN == 32) begin
|
||||
assign InitialWalkerState = L1_ADR;
|
||||
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
|
||||
// *** Possible bug - should be L1_ADR?
|
||||
assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
|
||||
end else begin
|
||||
logic GigapageMisaligned, TerapageMisaligned;
|
||||
assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR;
|
||||
assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
|
||||
assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
|
||||
assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
|
||||
assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
|
||||
end
|
||||
|
||||
// Initial state and misalignment for RV32/64
|
||||
if (`XLEN == 32) begin
|
||||
assign InitialWalkerState = L1_ADR;
|
||||
assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
|
||||
// *** Possible bug - should be L1_ADR?
|
||||
assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
|
||||
end else begin
|
||||
logic GigapageMisaligned, TerapageMisaligned;
|
||||
assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR;
|
||||
assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
|
||||
assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
|
||||
assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
|
||||
assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
|
||||
end
|
||||
|
||||
// Page Table Walker FSM
|
||||
// Page Table Walker FSM
|
||||
// If the setup time on the D$ RAM is short, it should be possible to merge the LEVELx_READ and LEVELx states
|
||||
// to decrease the latency of the HPTW. However, if the D$ is a cycle limiter, it's better to leave the
|
||||
// HPTW as shown below to keep the D$ setup time out of the critical path.
|
||||
// *** Is this really true. Talk with Ross. Seems like it's the next state logic on critical path instead.
|
||||
flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
|
||||
always_comb
|
||||
case (WalkerState)
|
||||
IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
|
||||
else NextWalkerState = IDLE;
|
||||
L3_ADR: NextWalkerState = L3_RD; // first access in SV48
|
||||
L3_RD: if (DCacheStall) NextWalkerState = L3_RD;
|
||||
else NextWalkerState = L2_ADR;
|
||||
// LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||
// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
|
||||
// else NextWalkerState = FAULT;
|
||||
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
|
||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
|
||||
else NextWalkerState = L1_ADR;
|
||||
// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||
// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
|
||||
// else NextWalkerState = FAULT;
|
||||
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
|
||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
|
||||
else NextWalkerState = L0_ADR;
|
||||
// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
|
||||
// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
|
||||
// else NextWalkerState = FAULT;
|
||||
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
||||
// else NextWalkerState = FAULT;
|
||||
LEAF: NextWalkerState = IDLE; // updates TLB
|
||||
default: begin
|
||||
// synthesis translate_off
|
||||
$error("Default state in HPTW should be unreachable");
|
||||
// synthesis translate_on
|
||||
NextWalkerState = IDLE; // should never be reached
|
||||
end
|
||||
endcase
|
||||
end else begin // No Virtual memory supported; tie HPTW outputs to 0
|
||||
assign HPTWRead = 0;
|
||||
assign HPTWAdr = 0;
|
||||
assign HPTWSize = 3'b000;
|
||||
end
|
||||
endgenerate
|
||||
case (WalkerState)
|
||||
IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
|
||||
else NextWalkerState = IDLE;
|
||||
L3_ADR: NextWalkerState = L3_RD; // first access in SV48
|
||||
L3_RD: if (DCacheStall) NextWalkerState = L3_RD;
|
||||
else NextWalkerState = L2_ADR;
|
||||
// LEVEL3: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF;
|
||||
// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
|
||||
// else NextWalkerState = FAULT;
|
||||
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
|
||||
else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
|
||||
else NextWalkerState = L1_ADR;
|
||||
// LEVEL2: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF;
|
||||
// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
|
||||
// else NextWalkerState = FAULT;
|
||||
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
|
||||
else if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
|
||||
else NextWalkerState = L0_ADR;
|
||||
// LEVEL1: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF;
|
||||
// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
|
||||
// else NextWalkerState = FAULT;
|
||||
L0_ADR: if (ValidLeafPTE & ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
|
||||
else NextWalkerState = LEAF;
|
||||
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
||||
// else NextWalkerState = FAULT;
|
||||
LEAF: NextWalkerState = IDLE; // updates TLB
|
||||
default: begin
|
||||
// synthesis translate_off
|
||||
$error("Default state in HPTW should be unreachable");
|
||||
// synthesis translate_on
|
||||
NextWalkerState = IDLE; // should never be reached
|
||||
end
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
@ -91,17 +91,20 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
|
||||
|
||||
// only instantiate TLB if Virtual Memory is supported
|
||||
generate
|
||||
if (`MEM_VIRTMEM) begin
|
||||
if (`MEM_VIRTMEM) begin:tlb
|
||||
logic ReadAccess, WriteAccess;
|
||||
assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages
|
||||
assign WriteAccess = WriteAccessM;
|
||||
tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU))
|
||||
tlb(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
|
||||
tlb(.clk, .reset,
|
||||
.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
|
||||
.SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
|
||||
.VAdr,
|
||||
.*);
|
||||
|
||||
end else begin // just pass address through as physical
|
||||
.VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
.PrivilegeModeW, .ReadAccess, .WriteAccess,
|
||||
.DisableTranslation, .PTE, .PageTypeWriteVal,
|
||||
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
|
||||
.Translate, .TLBPageFault);
|
||||
end else begin:tlb// just pass address through as physical
|
||||
assign Translate = 0;
|
||||
assign TLBMiss = 0;
|
||||
assign TLBHit = 1; // *** is this necessary
|
||||
@ -116,8 +119,15 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
|
||||
// Check physical memory accesses
|
||||
///////////////////////////////////////////
|
||||
|
||||
pmachecker pmachecker(.*);
|
||||
pmpchecker pmpchecker(.*);
|
||||
pmachecker pmachecker(.PhysicalAddress, .Size,
|
||||
.AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
|
||||
.Cacheable, .Idempotent, .AtomicAllowed,
|
||||
.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAccessFaultM);
|
||||
|
||||
pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.ExecuteAccessF, .WriteAccessM, .ReadAccessM,
|
||||
.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAccessFaultM);
|
||||
|
||||
// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
|
||||
// assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
|
||||
|
||||
@ -59,8 +59,8 @@ module pmachecker (
|
||||
|
||||
// Detect access faults
|
||||
assign PMAAccessFault = SelRegions[8] & AccessRWX;
|
||||
assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
|
||||
assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault;
|
||||
assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault;
|
||||
assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
|
||||
assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
|
||||
assign PMAStoreAccessFaultM = WriteAccessM & PMAAccessFault;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -61,7 +61,7 @@ module pmpadrdec (
|
||||
assign CurrentAdrFull = {PMPAdr[`PA_BITS-3:0], 2'b00};
|
||||
assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison
|
||||
assign PAgePMPAdrOut = ~PAltPMPAdr;
|
||||
assign TORMatch = PAgePMPAdrIn && PAltPMPAdr;
|
||||
assign TORMatch = PAgePMPAdrIn & PAltPMPAdr;
|
||||
|
||||
// Naturally aligned regions
|
||||
logic [`PA_BITS-1:0] NAMask, NABase;
|
||||
@ -75,7 +75,7 @@ module pmpadrdec (
|
||||
assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range
|
||||
|
||||
assign Match = (AdrMode == TOR) ? TORMatch :
|
||||
(AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch :
|
||||
(AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch :
|
||||
0;
|
||||
|
||||
assign L = PMPCfg[7] & FirstMatch;
|
||||
|
||||
@ -70,9 +70,9 @@ module pmpchecker (
|
||||
// Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
|
||||
assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active;
|
||||
|
||||
assign PMPInstrAccessFaultF = EnforcePMP && ExecuteAccessF && ~|X;
|
||||
assign PMPStoreAccessFaultM = EnforcePMP && WriteAccessM && ~|W;
|
||||
assign PMPLoadAccessFaultM = EnforcePMP && ReadAccessM && ~|R;
|
||||
assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|X;
|
||||
assign PMPStoreAccessFaultM = EnforcePMP & WriteAccessM & ~|W;
|
||||
assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|R;
|
||||
end else begin: pmpchecker // no checker
|
||||
assign PMPInstrAccessFaultF = 0;
|
||||
assign PMPLoadAccessFaultM = 0;
|
||||
|
||||
@ -61,7 +61,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
||||
assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G;
|
||||
|
||||
generate
|
||||
if (`XLEN == 32) begin
|
||||
if (`XLEN == 32) begin:match
|
||||
|
||||
assign {Key_ASID, Key1, Key0} = Key;
|
||||
assign {Query1, Query0} = VPN;
|
||||
@ -69,11 +69,11 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
||||
// Calculate the actual match value based on the input vpn and the page type.
|
||||
// For example, a megapage in SV32 only cares about VPN[1], so VPN[0]
|
||||
// should automatically match.
|
||||
assign Match0 = (Query0 == Key0) || (PageType[0]); // least signifcant section
|
||||
assign Match0 = (Query0 == Key0) | (PageType[0]); // least signifcant section
|
||||
assign Match1 = (Query1 == Key1);
|
||||
|
||||
assign Match = Match0 & Match1 & MatchASID & Valid;
|
||||
end else begin
|
||||
end else begin:match
|
||||
|
||||
logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3;
|
||||
logic Match2, Match3;
|
||||
@ -84,10 +84,10 @@ module tlbcamline #(parameter KEY_BITS = 20,
|
||||
// Calculate the actual match value based on the input vpn and the page type.
|
||||
// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
|
||||
// should automatically match.
|
||||
assign Match0 = (Query0 == Key0) || (PageType > 2'd0); // least signifcant section
|
||||
assign Match1 = (Query1 == Key1) || (PageType > 2'd1);
|
||||
assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
|
||||
assign Match3 = (Query3 == Key3) || SV39Mode; // this should always match in sv39 because they aren't used
|
||||
assign Match0 = (Query0 == Key0) | (PageType > 2'd0); // least signifcant section
|
||||
assign Match1 = (Query1 == Key1) | (PageType > 2'd1);
|
||||
assign Match2 = (Query2 == Key2) | (PageType > 2'd2);
|
||||
assign Match3 = (Query3 == Key3) | SV39Mode; // this should always match in sv39 because they aren't used
|
||||
|
||||
assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid;
|
||||
end
|
||||
|
||||
@ -65,7 +65,7 @@ module tlbcontrol #(parameter ITLB = 0) (
|
||||
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
|
||||
assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation;
|
||||
generate
|
||||
if (`XLEN==64) begin
|
||||
if (`XLEN==64) begin:rv64
|
||||
assign SV39Mode = (SATP_MODE == `SV39);
|
||||
// generate page fault if upper bits aren't all the same
|
||||
logic UpperEqual39, UpperEqual48;
|
||||
@ -90,33 +90,33 @@ module tlbcontrol #(parameter ITLB = 0) (
|
||||
|
||||
// Check whether the access is allowed, page faulting if not.
|
||||
generate
|
||||
if (ITLB == 1) begin // Instruction TLB fault checking
|
||||
if (ITLB == 1) begin:itlb // Instruction TLB fault checking
|
||||
logic ImproperPrivilege;
|
||||
|
||||
// User mode may only execute user mode pages, and supervisor mode may
|
||||
// only execute non-user mode pages.
|
||||
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) ||
|
||||
((EffectivePrivilegeMode == `S_MODE) && PTE_U);
|
||||
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
|
||||
((EffectivePrivilegeMode == `S_MODE) & PTE_U);
|
||||
// fault for software handling if access bit is off
|
||||
assign DAPageFault = ~PTE_A;
|
||||
assign TLBPageFault = (Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAPageFault || UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
|
||||
end else begin // Data TLB fault checking
|
||||
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
|
||||
end else begin:dtlb // Data TLB fault checking
|
||||
logic ImproperPrivilege, InvalidRead, InvalidWrite;
|
||||
|
||||
// User mode may only load/store from user mode pages, and supervisor mode
|
||||
// may only access user mode pages when STATUS_SUM is low.
|
||||
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) ||
|
||||
((EffectivePrivilegeMode == `S_MODE) && PTE_U && ~STATUS_SUM);
|
||||
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
|
||||
((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM);
|
||||
// Check for read error. Reads are invalid when the page is not readable
|
||||
// (and executable pages are not readable) or when the page is neither
|
||||
// readable nor executable (and executable pages are readable).
|
||||
assign InvalidRead = ReadAccess && ~PTE_R && (~STATUS_MXR | ~PTE_X);
|
||||
assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X);
|
||||
// Check for write error. Writes are invalid when the page's write bit is
|
||||
// low.
|
||||
assign InvalidWrite = WriteAccess && ~PTE_W;
|
||||
assign InvalidWrite = WriteAccess & ~PTE_W;
|
||||
// Fault for software handling if access bit is off or writing a page with dirty bit off
|
||||
assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D;
|
||||
assign TLBPageFault = (Translate && TLBHit && (ImproperPrivilege || InvalidRead || InvalidWrite || DAPageFault || UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
|
||||
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
@ -47,6 +47,6 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
|
||||
assign RUBitsAccessed = AccessLines | RUBits;
|
||||
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
|
||||
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
|
||||
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
|
||||
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
|
||||
// *** seems like enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
|
||||
endmodule
|
||||
|
||||
@ -61,7 +61,7 @@ module intdivrestoring (
|
||||
|
||||
// Handle sign extension for W-type instructions
|
||||
generate
|
||||
if (`XLEN == 64) begin // RV64 has W-type instructions
|
||||
if (`XLEN == 64) begin:rv64 // RV64 has W-type instructions
|
||||
mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
|
||||
mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
|
||||
end else begin // RV32 has no W-type instructions
|
||||
|
||||
@ -1,101 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// mul_cs.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 17 October 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Carry/Save Multiplier output with Wallace Reduction
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
module mult_cs #(parameter WIDTH = 8)
|
||||
(a, b, tc, sum, carry);
|
||||
|
||||
input logic [WIDTH-1:0] a;
|
||||
input logic [WIDTH-1:0] b;
|
||||
input logic tc;
|
||||
|
||||
output logic [2*WIDTH-1:0] sum;
|
||||
output logic [2*WIDTH-1:0] carry;
|
||||
|
||||
// PP array
|
||||
logic [2*WIDTH-1:0] pp_array [0:WIDTH-1];
|
||||
logic [2*WIDTH-1:0] next_pp_array [0:WIDTH-1];
|
||||
logic [2*WIDTH-1:0] tmp_sum, tmp_carry;
|
||||
logic [2*WIDTH-1:0] temp_pp;
|
||||
logic [2*WIDTH-1:0] tmp_pp_carry;
|
||||
logic [WIDTH-1:0] temp_b;
|
||||
logic temp_bitgroup;
|
||||
integer bit_pair, height, i;
|
||||
|
||||
always_comb
|
||||
begin
|
||||
// For each multiplicand PP generation
|
||||
for (bit_pair=0; bit_pair < WIDTH; bit_pair=bit_pair+1)
|
||||
begin
|
||||
// Shift to the right via P&H
|
||||
temp_b = (b >> (bit_pair));
|
||||
temp_bitgroup = temp_b[0];
|
||||
// PP generation
|
||||
case (temp_bitgroup)
|
||||
1'b0 : temp_pp = {2*WIDTH-1{1'b0}};
|
||||
1'b1 : temp_pp = a;
|
||||
default : temp_pp = {2*WIDTH-1{1'b0}};
|
||||
endcase
|
||||
// Shift to the left via P&H
|
||||
temp_pp = temp_pp << (bit_pair);
|
||||
pp_array[bit_pair] = temp_pp;
|
||||
end
|
||||
|
||||
// Height is multiplier
|
||||
height = WIDTH;
|
||||
|
||||
// Wallace Tree PP reduction
|
||||
while (height > 2)
|
||||
begin
|
||||
for (i=0; i < (height/3); i=i+1)
|
||||
begin
|
||||
next_pp_array[i*2] = pp_array[i*3]^pp_array[i*3+1]^pp_array[i*3+2];
|
||||
tmp_pp_carry = (pp_array[i*3] & pp_array[i*3+1]) |
|
||||
(pp_array[i*3+1] & pp_array[i*3+2]) |
|
||||
(pp_array[i*3] & pp_array[i*3+2]);
|
||||
next_pp_array[i*2+1] = tmp_pp_carry << 1;
|
||||
end
|
||||
// Reasssign not divisible by 3 rows to next_pp_array
|
||||
if ((height % 3) > 0)
|
||||
begin
|
||||
for (i=0; i < (height % 3); i=i+1)
|
||||
next_pp_array[2 * (height/3) + i] = pp_array[3 * (height/3) + i];
|
||||
end
|
||||
// Put back values in pp_array to start again
|
||||
for (i=0; i < WIDTH; i=i+1)
|
||||
pp_array[i] = next_pp_array[i];
|
||||
// Reduce height
|
||||
height = height - (height/3);
|
||||
end
|
||||
// Sum is first row in reduced array
|
||||
tmp_sum = pp_array[0];
|
||||
// Carry is second row in reduced array
|
||||
tmp_carry = pp_array[1];
|
||||
end
|
||||
|
||||
assign sum = tmp_sum;
|
||||
assign carry = tmp_carry;
|
||||
|
||||
endmodule // mult_cs
|
||||
|
||||
@ -39,21 +39,18 @@ module redundantmul #(parameter WIDTH =8)(
|
||||
|
||||
//
|
||||
|
||||
generate
|
||||
if (`DESIGN_COMPILER == 1)
|
||||
begin
|
||||
logic [2*WIDTH-1+2:0] tmp_out0; // DW02_
|
||||
logic [2*WIDTH-1+2:0] tmp_out1;
|
||||
DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1));
|
||||
assign out0 = tmp_out0[2*WIDTH-1:0];
|
||||
assign out1 = tmp_out1[2*WIDTH-1:0];
|
||||
end
|
||||
else if (`DESIGN_COMPILER == 2)
|
||||
mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
|
||||
else begin // force a nonredunant multipler. This will simulate properly and also is appropriate for FPGAs.
|
||||
assign out0 = a * b;
|
||||
assign out1 = 0;
|
||||
end
|
||||
generate
|
||||
if (`DESIGN_COMPILER == 1) begin:mul
|
||||
logic [2*WIDTH-1+2:0] tmp_out0;
|
||||
logic [2*WIDTH-1+2:0] tmp_out1;
|
||||
|
||||
DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1));
|
||||
assign out0 = tmp_out0[2*WIDTH-1:0];
|
||||
assign out1 = tmp_out1[2*WIDTH-1:0];
|
||||
end else begin:mul // force a nonredunant multipler. This will simulate properly and also is appropriate for FPGAs.
|
||||
assign out0 = a * b;
|
||||
assign out1 = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
@ -39,7 +39,7 @@ module csr #(parameter
|
||||
input logic [`XLEN-1:0] PCM, SrcAM,
|
||||
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
input logic InstrValidM, FRegWriteM, LoadStallD,
|
||||
input logic BPPredDirWrongM,
|
||||
input logic BTBPredPCWrongM,
|
||||
@ -108,26 +108,62 @@ module csr #(parameter
|
||||
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
|
||||
assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
|
||||
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
|
||||
assign CSRMWriteM = CSRWriteM && (PrivilegeModeW == `M_MODE);
|
||||
assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW);
|
||||
assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
|
||||
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
|
||||
assign CSRUWriteM = CSRWriteM;
|
||||
|
||||
csri csri(.*);
|
||||
csrsr csrsr(.*);
|
||||
csrc counters(.*);
|
||||
csrm csrm(.*); // Machine Mode CSRs
|
||||
csrs csrs(.*);
|
||||
csrn csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers
|
||||
csru csru(.*); // Floating Point Flags are part of User MOde
|
||||
csri csri(.clk, .reset, .StallW, .CSRMWriteM, .CSRSWriteM,
|
||||
.CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
|
||||
.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
|
||||
csrsr csrsr(.clk, .reset, .StallW,
|
||||
.WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM,
|
||||
.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
|
||||
.mretM, .sretM, .uretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM,
|
||||
.MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW,
|
||||
.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
|
||||
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM);
|
||||
csrc counters(.clk, .reset,
|
||||
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.InstrValidM, .LoadStallD, .CSRMWriteM,
|
||||
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess,
|
||||
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
|
||||
.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
|
||||
.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
|
||||
csrm csrm(.clk, .reset, .StallW,
|
||||
.CSRMWriteM, .MTrapM, .CSRAdrM,
|
||||
.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW,
|
||||
.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
|
||||
.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
|
||||
.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.MIP_REGW, .MIE_REGW, .WriteMSTATUSM,
|
||||
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
|
||||
csrs csrs(.clk, .reset, .StallW,
|
||||
.CSRSWriteM, .STrapM, .CSRAdrM,
|
||||
.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
|
||||
.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
|
||||
.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
|
||||
.SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW,
|
||||
.SATP_REGW, .SIP_REGW, .SIE_REGW,
|
||||
.WriteSSTATUSM, .IllegalCSRSAccessM);
|
||||
csrn csrn(.clk, .reset, .StallW,
|
||||
.CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM,
|
||||
.NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW,
|
||||
.CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW,
|
||||
.UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM);
|
||||
csru csru(.clk, .reset, .StallW,
|
||||
.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM,
|
||||
.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
|
||||
.IllegalCSRUAccessM);
|
||||
|
||||
// merge CSR Reads
|
||||
assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM;
|
||||
flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
|
||||
|
||||
// merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
|
||||
assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) ||
|
||||
(CSRAdrM[9:8] == 2'b01 && PrivilegeModeW == `U_MODE);
|
||||
assign IllegalCSRAccessM = ((IllegalCSRCAccessM && IllegalCSRMAccessM &&
|
||||
IllegalCSRSAccessM && IllegalCSRUAccessM && IllegalCSRNAccessM ||
|
||||
InsufficientCSRPrivilegeM) && CSRReadM) || IllegalCSRMWriteReadonlyM;
|
||||
assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) |
|
||||
(CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE);
|
||||
assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM &
|
||||
IllegalCSRSAccessM & IllegalCSRUAccessM & IllegalCSRNAccessM |
|
||||
InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
|
||||
endmodule
|
||||
|
||||
@ -27,48 +27,14 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes; overall this whole thing might need some rethinking
|
||||
module csrc #(parameter
|
||||
MCYCLE = 12'hB00,
|
||||
MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
|
||||
MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT
|
||||
MINSTRET = 12'hB02,
|
||||
MHPMCOUNTERBASE = 12'hB00,
|
||||
//MHPMCOUNTER3 = 12'hB03,
|
||||
//MHPMCOUNTER4 = 12'hB04,
|
||||
// ... more counters
|
||||
//MHPMCOUNTER31 = 12'hB1F,
|
||||
MCYCLEH = 12'hB80,
|
||||
MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
|
||||
MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT
|
||||
MINSTRETH = 12'hB82,
|
||||
MHPMCOUNTERHBASE = 12'hB80,
|
||||
//MHPMCOUNTER3H = 12'hB83,
|
||||
//MHPMCOUNTER4H = 12'hB84,
|
||||
// ... more counters
|
||||
//MHPMCOUNTER31H = 12'hB9F,
|
||||
MCOUNTERINHIBIT = 12'h320,
|
||||
MHPMEVENTBASE = 12'h320,
|
||||
//MHPMEVENT3 = 12'h323,
|
||||
//MHPMEVENT4 = 12'h324,
|
||||
// ... more counters
|
||||
//MHPMEVENT31 = 12'h33F,
|
||||
CYCLE = 12'hC00,
|
||||
TIME = 12'hC01,
|
||||
INSTRET = 12'hC02,
|
||||
HPMCOUNTERBASE = 12'hC00,
|
||||
//HPMCOUNTER3 = 12'hC03,
|
||||
//HPMCOUNTER4 = 12'hC04,
|
||||
// ...more counters
|
||||
//HPMCOUNTER31 = 12'hC1F,
|
||||
CYCLEH = 12'hC80,
|
||||
TIMEH = 12'hC81, // not specified
|
||||
INSTRETH = 12'hC82,
|
||||
HPMCOUNTERHBASE = 12'hC80
|
||||
//HPMCOUNTER3H = 12'hC83,
|
||||
//HPMCOUNTER4H = 12'hC84,
|
||||
// ... more counters
|
||||
//HPMCOUNTER31H = 12'hC9F
|
||||
HPMCOUNTERHBASE = 12'hC80,
|
||||
TIME = 12'hC01,
|
||||
TIMEH = 12'hC81
|
||||
) (
|
||||
input logic clk, reset,
|
||||
input logic StallE, StallM, StallW,
|
||||
@ -85,55 +51,40 @@ module csrc #(parameter
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
|
||||
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
output logic [`XLEN-1:0] CSRCReadValM,
|
||||
output logic IllegalCSRCAccessM
|
||||
);
|
||||
|
||||
generate
|
||||
if (`ZICOUNTERS_SUPPORTED) begin
|
||||
if (`ZICOUNTERS_SUPPORTED) begin:counters
|
||||
(* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
|
||||
logic [63:0] CYCLEPlusM, INSTRETPlusM;
|
||||
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
|
||||
logic [63:0] CYCLEPlusM, INSTRETPlusM;
|
||||
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
|
||||
logic WriteCYCLEM, WriteINSTRETM;
|
||||
logic [4:0] CounterNumM;
|
||||
logic [`XLEN-1:0] HPMCOUNTER_REGW [`COUNTERS-1:3];
|
||||
logic [`XLEN-1:0] HPMCOUNTERH_REGW [`COUNTERS-1:3];
|
||||
logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
|
||||
logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
|
||||
logic InstrValidNotFlushedM;
|
||||
logic LoadStallE, LoadStallM;
|
||||
logic [`COUNTERS-1:0] WriteHPMCOUNTERM;
|
||||
logic [`COUNTERS-1:0] CounterEvent;
|
||||
logic [63:0] HPMCOUNTERPlusM[`COUNTERS-1:0];
|
||||
logic [`XLEN-1:0] NextHPMCOUNTERM[`COUNTERS-1:0];
|
||||
genvar i;
|
||||
|
||||
// Interface signals
|
||||
flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
|
||||
flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
|
||||
assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
|
||||
|
||||
// Write enables
|
||||
assign WriteCYCLEM = CSRMWriteM && (CSRAdrM == MCYCLE);
|
||||
assign WriteINSTRETM = CSRMWriteM && (CSRAdrM == MINSTRET);
|
||||
|
||||
// Counter adders with inhibits for power savings
|
||||
assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
|
||||
assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidNotFlushedM & ~MCOUNTINHIBIT_REGW[2]};
|
||||
assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
|
||||
assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0];
|
||||
|
||||
// parameterized number of additional counters
|
||||
if (`COUNTERS > 3) begin
|
||||
logic [`COUNTERS-1:3] WriteHPMCOUNTERM;
|
||||
logic [`COUNTERS-1:0] CounterEvent;
|
||||
logic [63:0] /*HPMCOUNTER_REGW[`COUNTERS-1:3], */ HPMCOUNTERPlusM[`COUNTERS-1:3];
|
||||
logic [`XLEN-1:0] NextHPMCOUNTERM[`COUNTERS-1:3];
|
||||
genvar i;
|
||||
|
||||
// could replace special counters 0-2 with this loop for all counters
|
||||
assign CounterEvent[0] = 1'b1;
|
||||
assign CounterEvent[1] = 1'b0;
|
||||
if(`QEMU) begin
|
||||
assign CounterEvent[`COUNTERS-1:2] = 0;
|
||||
end else begin
|
||||
|
||||
logic LoadStallE, LoadStallM;
|
||||
|
||||
flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
|
||||
flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
|
||||
|
||||
assign CounterEvent[2] = InstrValidNotFlushedM;
|
||||
// Determine when to increment each counter
|
||||
assign CounterEvent[0] = 1'b1; // MCYCLE always increments
|
||||
assign CounterEvent[1] = 1'b0; // Counter 0 doesn't exist
|
||||
assign CounterEvent[2] = InstrValidNotFlushedM;
|
||||
if(`QEMU) begin // No other performance counters in QEMU
|
||||
assign CounterEvent[`COUNTERS-1:3] = 0;
|
||||
end else begin // User-defined counters
|
||||
assign CounterEvent[3] = LoadStallM; // don't want to suppress on flush as this only happens if flushed.
|
||||
assign CounterEvent[4] = BPPredDirWrongM & InstrValidNotFlushedM;
|
||||
assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
|
||||
@ -147,120 +98,73 @@ module csrc #(parameter
|
||||
assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
|
||||
end
|
||||
|
||||
for (i = 3; i < `COUNTERS; i = i+1) begin
|
||||
assign WriteHPMCOUNTERM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERBASE + i);
|
||||
assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
|
||||
always @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
|
||||
if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
|
||||
else HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
|
||||
// Counter update and write logic
|
||||
for (i = 0; i < `COUNTERS; i = i+1) begin
|
||||
assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
|
||||
assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
|
||||
always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
|
||||
if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
|
||||
else HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
|
||||
|
||||
if (`XLEN==32) begin
|
||||
logic [`COUNTERS-1:3] WriteHPMCOUNTERHM;
|
||||
logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:3];
|
||||
assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
|
||||
assign WriteHPMCOUNTERHM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERHBASE + i);
|
||||
assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
|
||||
always @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
|
||||
if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
|
||||
else HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
|
||||
end else begin
|
||||
assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
if (`XLEN==32) begin // write high and low separately
|
||||
logic [`COUNTERS-1:0] WriteHPMCOUNTERHM;
|
||||
logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:0];
|
||||
assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
|
||||
assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
|
||||
assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
|
||||
always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
|
||||
if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
|
||||
else HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
|
||||
end else begin // XLEN=64; write entire register
|
||||
assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
|
||||
end
|
||||
end
|
||||
|
||||
// Write / update counters
|
||||
// Only the Machine mode versions of the counter CSRs are writable
|
||||
if (`XLEN==64) begin// 64-bit counters
|
||||
flopr #(64) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW);
|
||||
flopr #(64) INSTRETreg(clk, reset, NextINSTRETM, INSTRET_REGW);
|
||||
end else begin // 32-bit low and high counters
|
||||
logic WriteTIMEHM, WriteTIMECMPHM, WriteCYCLEHM, WriteINSTRETHM;
|
||||
logic [`XLEN-1:0] NextCYCLEHM, NextTIMEHM, NextINSTRETHM;
|
||||
|
||||
// Write Enables
|
||||
assign WriteCYCLEHM = CSRMWriteM && (CSRAdrM == MCYCLEH);
|
||||
assign WriteINSTRETHM = CSRMWriteM && (CSRAdrM == MINSTRETH);
|
||||
assign NextCYCLEHM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[63:32];
|
||||
assign NextINSTRETHM = WriteINSTRETHM ? CSRWriteValM : INSTRETPlusM[63:32];
|
||||
|
||||
// Counter CSRs
|
||||
flopr #(32) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW[31:0]);
|
||||
flopr #(32) INSTRETreg(clk, reset, NextINSTRETM, INSTRET_REGW[31:0]);
|
||||
flopr #(32) CYCLEHreg(clk, reset, NextCYCLEHM, CYCLE_REGW[63:32]);
|
||||
flopr #(32) INSTRETHreg(clk, reset, NextINSTRETHM, INSTRET_REGW[63:32]);
|
||||
end
|
||||
|
||||
// eventually move TIME and TIMECMP to the CLINT -- Ben 06/17/21: sure let's give that a shot!
|
||||
// run TIME off asynchronous reference clock
|
||||
// synchronize write enable to TIME
|
||||
// four phase handshake to synchronize reads from TIME
|
||||
|
||||
// interrupt on timer compare
|
||||
// ability to disable optional CSRs
|
||||
|
||||
// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
|
||||
assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
|
||||
if (`XLEN==64) // 64-bit counter reads
|
||||
always_comb
|
||||
if (PrivilegeModeW == `M_MODE ||
|
||||
MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
|
||||
IllegalCSRCAccessM = 0;
|
||||
if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE];
|
||||
else case (CSRAdrM)
|
||||
MTIME: CSRCReadValM = MTIME_CLINT;
|
||||
MTIMECMP: CSRCReadValM = MTIMECMP_CLINT;
|
||||
MCYCLE: CSRCReadValM = CYCLE_REGW;
|
||||
MINSTRET: CSRCReadValM = INSTRET_REGW;
|
||||
TIME: CSRCReadValM = MTIME_CLINT;
|
||||
CYCLE: CSRCReadValM = CYCLE_REGW;
|
||||
INSTRET: CSRCReadValM = INSTRET_REGW;
|
||||
default: begin
|
||||
CSRCReadValM = 0;
|
||||
IllegalCSRCAccessM = 1;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
CSRCReadValM = 0;
|
||||
always_comb
|
||||
if (PrivilegeModeW == `M_MODE |
|
||||
MCOUNTEREN_REGW[CounterNumM] & (!`S_SUPPORTED | PrivilegeModeW == `S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
|
||||
IllegalCSRCAccessM = 0;
|
||||
if (`XLEN==64) begin // 64-bit counter reads
|
||||
// Veri lator doesn't realize this only occurs for XLEN=64
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = 0;
|
||||
IllegalCSRCAccessM = 1; // requested CSR doesn't exist
|
||||
end
|
||||
else // 32-bit counter reads
|
||||
always_comb
|
||||
if (PrivilegeModeW == `M_MODE || MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin
|
||||
IllegalCSRCAccessM = 0;
|
||||
if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE];
|
||||
else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE];
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE];
|
||||
else case (CSRAdrM)
|
||||
MTIME: CSRCReadValM = MTIME_CLINT[31:0];
|
||||
MTIMECMP: CSRCReadValM = MTIMECMP_CLINT[31:0];
|
||||
MCYCLE: CSRCReadValM = CYCLE_REGW[31:0];
|
||||
MINSTRET: CSRCReadValM = INSTRET_REGW[31:0];
|
||||
TIME: CSRCReadValM = MTIME_CLINT[31:0];
|
||||
CYCLE: CSRCReadValM = CYCLE_REGW[31:0];
|
||||
INSTRET: CSRCReadValM = INSTRET_REGW[31:0];
|
||||
MTIMEH: CSRCReadValM = MTIME_CLINT[63:32];
|
||||
MTIMECMPH: CSRCReadValM = MTIMECMP_CLINT[63:32];
|
||||
MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
|
||||
MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
|
||||
TIMEH: CSRCReadValM = MTIME_CLINT[63:32];
|
||||
CYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
|
||||
INSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
|
||||
default: begin
|
||||
CSRCReadValM = 0;
|
||||
IllegalCSRCAccessM = 1;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
end else begin // 32-bit counter reads
|
||||
// Veri lator doesn't realize this only occurs for XLEN=32
|
||||
/* verilator lint_off WIDTH */
|
||||
if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
|
||||
else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
|
||||
/* verilator lint_on WIDTH */
|
||||
else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
|
||||
else begin
|
||||
CSRCReadValM = 0;
|
||||
end
|
||||
IllegalCSRCAccessM = 1; // requested CSR doesn't exist
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
CSRCReadValM = 0;
|
||||
IllegalCSRCAccessM = 1; // no privileges for this csr
|
||||
end
|
||||
end else begin
|
||||
assign CSRCReadValM = 0;
|
||||
assign IllegalCSRCAccessM = 1;
|
||||
assign IllegalCSRCAccessM = 1; // counters aren't enabled
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
// To Do:
|
||||
// review couunter spec
|
||||
// upper unimplemented counters should read as 0 rather than illegal access
|
||||
// mounteren should only exist if u-mode exists
|
||||
// Implement MHPMEVENT
|
||||
|
||||
@ -61,20 +61,20 @@ module csri #(parameter
|
||||
end
|
||||
|
||||
// Interrupt Write Enables
|
||||
assign WriteMIPM = CSRMWriteM && (CSRAdrM == MIP) && ~StallW;
|
||||
assign WriteMIEM = CSRMWriteM && (CSRAdrM == MIE) && ~StallW;
|
||||
assign WriteSIPM = CSRSWriteM && (CSRAdrM == SIP) && ~StallW;
|
||||
assign WriteSIEM = CSRSWriteM && (CSRAdrM == SIE) && ~StallW;
|
||||
assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & ~StallW;
|
||||
assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & ~StallW;
|
||||
assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & ~StallW;
|
||||
assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & ~StallW;
|
||||
|
||||
// Interrupt Pending and Enable Registers
|
||||
// MEIP, MTIP, MSIP are read-only
|
||||
// SEIP, STIP, SSIP is writable in MIP if S mode exists
|
||||
// SSIP is writable in SIP if S mode exists
|
||||
generate
|
||||
if (`S_SUPPORTED) begin
|
||||
if (`S_SUPPORTED) begin:mask
|
||||
assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9)
|
||||
assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3)
|
||||
end else begin
|
||||
end else begin:mask
|
||||
assign MIP_WRITE_MASK = 12'h000;
|
||||
assign SIP_WRITE_MASK = 12'h000;
|
||||
end
|
||||
@ -93,7 +93,7 @@ module csri #(parameter
|
||||
|
||||
// restricted views of registers
|
||||
generate
|
||||
always_comb begin
|
||||
always_comb begin:regs
|
||||
// Add MEIP read-only signal
|
||||
IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
|
||||
|
||||
|
||||
@ -128,18 +128,18 @@ module csrm #(parameter
|
||||
assign MHARTID_REGW = 0;
|
||||
|
||||
// Write machine Mode CSRs
|
||||
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS) && ~StallW;
|
||||
assign WriteMTVECM = CSRMWriteM && (CSRAdrM == MTVEC) && ~StallW;
|
||||
assign WriteMEDELEGM = CSRMWriteM && (CSRAdrM == MEDELEG) && ~StallW;
|
||||
assign WriteMIDELEGM = CSRMWriteM && (CSRAdrM == MIDELEG) && ~StallW;
|
||||
assign WriteMSCRATCHM = CSRMWriteM && (CSRAdrM == MSCRATCH) && ~StallW;
|
||||
assign WriteMEPCM = MTrapM | (CSRMWriteM && (CSRAdrM == MEPC)) && ~StallW;
|
||||
assign WriteMCAUSEM = MTrapM | (CSRMWriteM && (CSRAdrM == MCAUSE)) && ~StallW;
|
||||
assign WriteMTVALM = MTrapM | (CSRMWriteM && (CSRAdrM == MTVAL)) && ~StallW;
|
||||
assign WriteMCOUNTERENM = CSRMWriteM && (CSRAdrM == MCOUNTEREN) && ~StallW;
|
||||
assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT) && ~StallW;
|
||||
assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & ~StallW;
|
||||
assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & ~StallW;
|
||||
assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & ~StallW;
|
||||
assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & ~StallW;
|
||||
assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & ~StallW;
|
||||
assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & ~StallW;
|
||||
assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & ~StallW;
|
||||
assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & ~StallW;
|
||||
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & ~StallW;
|
||||
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & ~StallW;
|
||||
|
||||
assign IllegalCSRMWriteReadonlyM = CSRMWriteM && (CSRAdrM == MVENDORID || CSRAdrM == MARCHID || CSRAdrM == MIMPID || CSRAdrM == MHARTID);
|
||||
assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
|
||||
|
||||
// CSRs
|
||||
flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0
|
||||
@ -173,11 +173,11 @@ module csrm #(parameter
|
||||
logic [5:0] entry;
|
||||
always_comb begin
|
||||
entry = '0;
|
||||
IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &&
|
||||
(CSRAdrM == MEDELEG || CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
|
||||
if (CSRAdrM >= PMPADDR0 && CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
|
||||
IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &
|
||||
(CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
|
||||
if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
|
||||
CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0];
|
||||
else if (CSRAdrM >= PMPCFG0 && CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
|
||||
else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
|
||||
if (`XLEN==64) begin
|
||||
entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64
|
||||
CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+7],PMPCFG_ARRAY_REGW[entry+6],PMPCFG_ARRAY_REGW[entry+5],PMPCFG_ARRAY_REGW[entry+4],
|
||||
|
||||
@ -50,7 +50,7 @@ module csrn #(parameter
|
||||
|
||||
// User mode CSRs below only needed when user mode traps are supported
|
||||
generate
|
||||
if (`N_SUPPORTED) begin
|
||||
if (`N_SUPPORTED) begin:nmode
|
||||
logic WriteUTVECM;
|
||||
logic WriteUSCRATCHM, WriteUEPCM;
|
||||
logic WriteUCAUSEM, WriteUTVALM;
|
||||
@ -58,11 +58,11 @@ module csrn #(parameter
|
||||
logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
|
||||
|
||||
// Write enables
|
||||
assign WriteUSTATUSM = CSRNWriteM && (CSRAdrM == USTATUS) && ~StallW;
|
||||
assign WriteUTVECM = CSRNWriteM && (CSRAdrM == UTVEC) && ~StallW;
|
||||
assign WriteUEPCM = UTrapM | (CSRNWriteM && (CSRAdrM == UEPC)) && ~StallW;
|
||||
assign WriteUCAUSEM = UTrapM | (CSRNWriteM && (CSRAdrM == UCAUSE)) && ~StallW;
|
||||
assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL)) && ~StallW;
|
||||
assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & ~StallW;
|
||||
assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & ~StallW;
|
||||
assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & ~StallW;
|
||||
assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & ~StallW;
|
||||
assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & ~StallW;
|
||||
|
||||
// CSRs
|
||||
flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW);
|
||||
|
||||
@ -70,21 +70,21 @@ module csrs #(parameter
|
||||
|
||||
// Supervisor mode CSRs sometimes supported
|
||||
generate
|
||||
if (`S_SUPPORTED) begin
|
||||
if (`S_SUPPORTED) begin:csrs
|
||||
logic WriteSTVECM;
|
||||
logic WriteSSCRATCHM, WriteSEPCM;
|
||||
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
|
||||
logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
|
||||
|
||||
assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS) && ~StallW;
|
||||
assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC) && ~StallW;
|
||||
assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH) && ~StallW;
|
||||
assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC)) && ~StallW;
|
||||
assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE)) && ~StallW;
|
||||
assign WriteSTVALM = STrapM | (CSRSWriteM && (CSRAdrM == STVAL)) && ~StallW;
|
||||
assign WriteSATPM = CSRSWriteM && (CSRAdrM == SATP) && (PrivilegeModeW == `M_MODE || ~STATUS_TVM) && ~StallW;
|
||||
assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN) && ~StallW;
|
||||
assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & ~StallW;
|
||||
assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & ~StallW;
|
||||
assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & ~StallW;
|
||||
assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & ~StallW;
|
||||
assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & ~StallW;
|
||||
assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & ~StallW;
|
||||
assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & ~StallW;
|
||||
assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & ~StallW;
|
||||
|
||||
// CSRs
|
||||
flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); //busybear: change reset to 0
|
||||
@ -96,16 +96,17 @@ module csrs #(parameter
|
||||
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
|
||||
else
|
||||
assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
|
||||
if (`BUSYBEAR == 1)
|
||||
if (`BUSYBEAR == 1) begin:scounteren
|
||||
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, SCOUNTEREN_REGW);
|
||||
else if (`BUILDROOT == 1)
|
||||
end else if (`BUILDROOT == 1) begin:scounteren
|
||||
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
|
||||
else
|
||||
end else begin:scounteren
|
||||
flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
|
||||
if (`N_SUPPORTED) begin
|
||||
end
|
||||
if (`N_SUPPORTED) begin:nregs
|
||||
logic WriteSEDELEGM, WriteSIDELEGM;
|
||||
assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);
|
||||
assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG);
|
||||
assign WriteSEDELEGM = CSRSWriteM & (CSRAdrM == SEDELEG);
|
||||
assign WriteSIDELEGM = CSRSWriteM & (CSRAdrM == SIDELEG);
|
||||
flopenr #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, SEDELEG_REGW);
|
||||
flopenr #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, SIDELEG_REGW);
|
||||
end else begin
|
||||
@ -114,8 +115,8 @@ module csrs #(parameter
|
||||
end
|
||||
|
||||
// CSR Reads
|
||||
always_comb begin
|
||||
IllegalCSRSAccessM = !(`N_SUPPORTED) && (CSRAdrM == SEDELEG || CSRAdrM == SIDELEG); // trap on DELEG register access when no N-mode
|
||||
always_comb begin:csrr
|
||||
IllegalCSRSAccessM = !(`N_SUPPORTED) & (CSRAdrM == SEDELEG | CSRAdrM == SIDELEG); // trap on DELEG register access when no N-mode
|
||||
case (CSRAdrM)
|
||||
SSTATUS: CSRSReadValM = SSTATUS_REGW;
|
||||
STVEC: CSRSReadValM = STVEC_REGW;
|
||||
@ -129,7 +130,7 @@ module csrs #(parameter
|
||||
SEPC: CSRSReadValM = SEPC_REGW;
|
||||
SCAUSE: CSRSReadValM = SCAUSE_REGW;
|
||||
STVAL: CSRSReadValM = STVAL_REGW;
|
||||
SATP: if (`MEM_VIRTMEM && (PrivilegeModeW == `M_MODE || ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
|
||||
SATP: if (`MEM_VIRTMEM & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
|
||||
else begin
|
||||
CSRSReadValM = 0;
|
||||
if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1;
|
||||
|
||||
@ -96,14 +96,14 @@ module csrsr (
|
||||
assign STATUS_UXL = `U_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if user mode supported
|
||||
assign STATUS_SUM = `S_SUPPORTED & `MEM_VIRTMEM & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
|
||||
assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
|
||||
assign STATUS_FS = (`S_SUPPORTED && (`F_SUPPORTED || `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP
|
||||
assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP
|
||||
endgenerate
|
||||
assign STATUS_SD = (STATUS_FS == 2'b11) || (STATUS_XS == 2'b11); // dirty state logic
|
||||
assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
|
||||
assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty
|
||||
|
||||
always_comb
|
||||
if (CSRWriteValM[12:11] == `U_MODE && `U_SUPPORTED) STATUS_MPP_NEXT = `U_MODE;
|
||||
else if (CSRWriteValM[12:11] == `S_MODE && `S_SUPPORTED) STATUS_MPP_NEXT = `S_MODE;
|
||||
if (CSRWriteValM[12:11] == `U_MODE & `U_SUPPORTED) STATUS_MPP_NEXT = `U_MODE;
|
||||
else if (CSRWriteValM[12:11] == `S_MODE & `S_SUPPORTED) STATUS_MPP_NEXT = `S_MODE;
|
||||
else STATUS_MPP_NEXT = `M_MODE;
|
||||
|
||||
// registers for STATUS bits
|
||||
|
||||
@ -45,15 +45,15 @@ module csru #(parameter
|
||||
|
||||
// Floating Point CSRs in User Mode only needed if Floating Point is supported
|
||||
generate
|
||||
if (`F_SUPPORTED | `D_SUPPORTED) begin
|
||||
if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
|
||||
logic [4:0] FFLAGS_REGW;
|
||||
logic [2:0] NextFRMM;
|
||||
logic [4:0] NextFFLAGSM;
|
||||
|
||||
// Write enables
|
||||
//assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR) && ~StallW;
|
||||
assign WriteFRMM = (CSRUWriteM && (CSRAdrM == FRM | CSRAdrM == FCSR)) && ~StallW;
|
||||
assign WriteFFLAGSM = (CSRUWriteM && (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) && ~StallW;
|
||||
//assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & ~StallW;
|
||||
assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR)) & ~StallW;
|
||||
assign WriteFFLAGSM = (CSRUWriteM & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & ~StallW;
|
||||
|
||||
// Write Values
|
||||
assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
|
||||
|
||||
@ -54,7 +54,7 @@ module privileged (
|
||||
input logic LoadMisalignedFaultM,
|
||||
input logic StoreMisalignedFaultM,
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
||||
input logic [4:0] SetFflagsM,
|
||||
|
||||
@ -153,14 +153,13 @@ module privileged (
|
||||
///////////////////////////////////////////
|
||||
// Control and Status Registers
|
||||
///////////////////////////////////////////
|
||||
//csr csr(.*);
|
||||
csr csr(.clk, .reset,
|
||||
.FlushE, .FlushM, .FlushW,
|
||||
.StallE, .StallM, .StallW,
|
||||
.InstrM, .PCM, .SrcAM,
|
||||
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM,
|
||||
.TimerIntM, .ExtIntM, .SwIntM,
|
||||
.MTIME_CLINT, .MTIMECMP_CLINT,
|
||||
.MTIME_CLINT,
|
||||
.InstrValidM, .FRegWriteM, .LoadStallD,
|
||||
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
|
||||
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,
|
||||
@ -216,7 +215,6 @@ module privileged (
|
||||
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
|
||||
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
|
||||
// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
|
||||
//trap trap(.*);
|
||||
trap trap(.clk, .reset,
|
||||
.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
|
||||
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
||||
|
||||
@ -62,8 +62,8 @@ module trap (
|
||||
// interrupt if any sources are pending
|
||||
// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
|
||||
// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
|
||||
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
|
||||
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
|
||||
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
|
||||
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
|
||||
assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
|
||||
assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
|
||||
assign InterruptM = PendingInterruptM & ~CommittedM;
|
||||
@ -104,9 +104,9 @@ module trap (
|
||||
// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
|
||||
// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
|
||||
generate
|
||||
if(`VECTORED_INTERRUPTS_SUPPORTED) begin
|
||||
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
|
||||
always_comb
|
||||
if (PrivilegedTrapVector[1:0] == 2'b01 && CauseM[`XLEN-1] == 1)
|
||||
if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1)
|
||||
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {CauseM[`XLEN-5:0], 2'b00}, 2'b00};
|
||||
else
|
||||
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module clint (
|
||||
input logic HCLK, HRESETn,
|
||||
input logic HCLK, HRESETn, TIMECLK,
|
||||
input logic HSELCLINT,
|
||||
input logic [15:0] HADDR,
|
||||
input logic HWRITE,
|
||||
@ -36,7 +36,7 @@ module clint (
|
||||
input logic [1:0] HTRANS,
|
||||
output logic [`XLEN-1:0] HREADCLINT,
|
||||
output logic HRESPCLINT, HREADYCLINT,
|
||||
output logic [63:0] MTIME, MTIMECMP,
|
||||
output logic [63:0] MTIME,
|
||||
output logic TimerIntM, SwIntM);
|
||||
|
||||
logic MSIP;
|
||||
@ -44,6 +44,7 @@ module clint (
|
||||
logic [15:0] entry, entryd;
|
||||
logic memwrite;
|
||||
logic initTrans;
|
||||
logic [63:0] MTIMECMP;
|
||||
|
||||
assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
|
||||
// entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
|
||||
@ -51,7 +52,7 @@ module clint (
|
||||
flopr #(16) entrydflop(HCLK, ~HRESETn, entry, entryd);
|
||||
|
||||
assign HRESPCLINT = 0; // OK
|
||||
assign HREADYCLINT = 1'b1; // will need to be modified if CLINT ever needs more than 1 cycle to do something
|
||||
assign HREADYCLINT = 1'b1; // *** needs to depend on DONE during accesses
|
||||
|
||||
// word aligned reads
|
||||
generate
|
||||
@ -69,7 +70,7 @@ module clint (
|
||||
|
||||
// register access
|
||||
generate
|
||||
if (`XLEN==64) begin
|
||||
if (`XLEN==64) begin:clint // 64-bit
|
||||
always @(posedge HCLK) begin
|
||||
case(entry)
|
||||
16'h0000: HREADCLINT <= {63'b0, MSIP};
|
||||
@ -81,23 +82,25 @@ module clint (
|
||||
always_ff @(posedge HCLK or negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
MSIP <= 0;
|
||||
MTIMECMP <= (64)'(0);
|
||||
MTIMECMP <= 0;
|
||||
// MTIMECMP is not reset
|
||||
end else if (memwrite) begin
|
||||
if (entryd == 16'h0000) MSIP <= HWDATA[0];
|
||||
if (entryd == 16'h4000) MTIMECMP <= HWDATA;
|
||||
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
|
||||
end
|
||||
|
||||
// eventually replace MTIME logic below with timereg
|
||||
// timereg tr(HCLK, HRESETn, TIMECLK, memwrite & (entryd==16'hBFF8), 1'b0, HWDATA, MTIME, done);
|
||||
|
||||
always_ff @(posedge HCLK or negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
MTIME <= 0;
|
||||
// MTIMECMP is not reset
|
||||
end else if (memwrite & entryd == 16'hBFF8) begin
|
||||
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
|
||||
MTIME <= HWDATA;
|
||||
end else MTIME <= MTIME + 1;
|
||||
end else begin // 32-bit
|
||||
MTIME <= HWDATA;
|
||||
end else MTIME <= MTIME + 1;
|
||||
end else begin:clint // 32-bit
|
||||
always @(posedge HCLK) begin
|
||||
case(entry)
|
||||
16'h0000: HREADCLINT <= {31'b0, MSIP};
|
||||
@ -111,26 +114,28 @@ module clint (
|
||||
always_ff @(posedge HCLK or negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
MSIP <= 0;
|
||||
MTIMECMP <= (64)'(0);
|
||||
// MTIMECMP is not reset
|
||||
MTIMECMP <= 0;
|
||||
// MTIMECMP is not reset ***?
|
||||
end else if (memwrite) begin
|
||||
if (entryd == 16'h0000) MSIP <= HWDATA[0];
|
||||
if (entryd == 16'h4000) MTIMECMP[31:0] <= HWDATA;
|
||||
if (entryd == 16'h4004) MTIMECMP[63:32] <= HWDATA;
|
||||
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
|
||||
end
|
||||
end
|
||||
|
||||
// eventually replace MTIME logic below with timereg
|
||||
// timereg tr(HCLK, HRESETn, TIMECLK, memwrite & (entryd==16'hBFF8), memwrite & (entryd == 16'hBFFC), HWDATA, MTIME, done);
|
||||
always_ff @(posedge HCLK or negedge HRESETn)
|
||||
if (~HRESETn) begin
|
||||
MTIME <= 0;
|
||||
// MTIMECMP is not reset
|
||||
end else if (memwrite & (entryd == 16'hBFF8)) begin
|
||||
MTIME[31:0] <= HWDATA;
|
||||
end else if (memwrite & (entryd == 16'hBFFC)) begin
|
||||
end else if (memwrite & (entryd == 16'hBFF8)) begin
|
||||
MTIME[31:0] <= HWDATA;
|
||||
end else if (memwrite & (entryd == 16'hBFFC)) begin
|
||||
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
|
||||
MTIME[63:32]<= HWDATA;
|
||||
end else MTIME <= MTIME + 1;
|
||||
end
|
||||
MTIME[63:32]<= HWDATA;
|
||||
end else MTIME <= MTIME + 1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Software interrupt when MSIP is set
|
||||
@ -140,3 +145,102 @@ module clint (
|
||||
|
||||
endmodule
|
||||
|
||||
module timeregsync(
|
||||
input logic clk, resetn,
|
||||
input logic we0, we1,
|
||||
input logic [`XLEN-1:0] wd,
|
||||
output logic [63:0] q);
|
||||
|
||||
if (`XLEN==64)
|
||||
always_ff @(posedge clk or negedge resetn)
|
||||
if (~resetn) q <= 0;
|
||||
else if (we0) q <= wd;
|
||||
else q <= q + 1;
|
||||
else
|
||||
always_ff @(posedge clk or negedge resetn)
|
||||
if (~resetn) q <= 0;
|
||||
else if (we0) q[31:0] <= wd;
|
||||
else if (we1) q[63:32] <= wd;
|
||||
else q <= q + 1;
|
||||
endmodule
|
||||
|
||||
module timereg(
|
||||
input logic HCLK, HRESETn, TIMECLK,
|
||||
input logic we0, we1,
|
||||
input logic [`XLEN-1:0] HWDATA,
|
||||
output logic [63:0] MTIME,
|
||||
output logic done);
|
||||
|
||||
// if (`TIMEBASE_SYNC) begin:timereg // use HCLK for MTIME
|
||||
if (1) begin:timereg // use HCLK for MTIME
|
||||
timregsync timeregsync(.clk(HCLK), .resetn(HRESETn), .we0, .we1, .wd(HWDATA), .q(MTIME));
|
||||
assign done = 1; // immediately completes
|
||||
end else begin // use asynchronous TIMECLK
|
||||
// TIME counter runs on TIMECLK but bus interface runs on HCLK
|
||||
// Need to synchronize reads and writes
|
||||
// This is subtle because synchronizing a binary counter on a per-bit basis could give a mix of old and new bits
|
||||
// Instead, we use a Gray coded counter that only changes one bit per cycle
|
||||
// Synchronizing this for a read is safe because we are guaranteed to get either the old or the new value.
|
||||
// Writing to the counter requires a request/acknowledge handshake to ensure the write value is held long enough.
|
||||
// The handshake signals are synchronized in each direction across the interface
|
||||
// There is no back pressure on instructions, so if multiple counter writes occur ***
|
||||
|
||||
logic req, req_sync, ack, we0_stored, we1_stored, ack_stored, resetn_sync;
|
||||
logic [`XLEN-1:0] wd_stored;
|
||||
logic [63:0] time_int, time_int_gc, time_gc, MTIME_GC;
|
||||
|
||||
// When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged
|
||||
// When the acknowledge falls, the transaction is done and the system is ready for another write.
|
||||
// ***look at redoing this assuming write enable and data are held rather than pulsed.
|
||||
always_ff @(posedge HCLK or negedge HRESETn)
|
||||
if (~HRESETn)
|
||||
req <= 0; // don't bother resetting wd
|
||||
else begin
|
||||
req <= we0 | we1 | req & ~ack;
|
||||
we0_stored <= we0;
|
||||
we1_stored <= we1;
|
||||
wd_stored <= HWDATA;
|
||||
ack_stored <= ack;
|
||||
done <= ack_stored & ~ack;
|
||||
end
|
||||
|
||||
// synchronize the reset and reqest into the TIMECLK domain
|
||||
sync resetsync(TIMECLK, HRESETn, resetn_sync);
|
||||
sync rsync(TIMECLK, req, req_sync);
|
||||
// synchronize the acknowledge back to the HCLK domain to indicate the request was handled and can be lowered
|
||||
sync async(HCLK, req_sync, ack);
|
||||
|
||||
timeregsync timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int));
|
||||
binarytogray b2g(time_int, time_int_gc);
|
||||
flop gcreg(TIMECLK, time_int_gc, time_gc);
|
||||
|
||||
sync timesync[63:0](HCLK, time_gc, MTIME_GC);
|
||||
graytobinary g2b(MTIME_GC, MTIME);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module binarytogray #(parameter N = `XLEN) (
|
||||
input logic [N-1:0] b,
|
||||
output logic [N-1:0] g);
|
||||
|
||||
// G[N-1] = B[N-1]; G[i] = B[i] ^ B[i+1] for 0 <= i < N-1
|
||||
// requires single layer of N-1 XOR gates
|
||||
assign g = b ^ {1'b0, b[N-1:1]};
|
||||
endmodule
|
||||
|
||||
module graytobinary #(parameter N = `XLEN) (
|
||||
input logic [N-1:0] g,
|
||||
output logic [N-1:0] b);
|
||||
|
||||
// B[N-1] = G[N-1]; B[i] = G[i] ^ B[i+1] for 0 <= i < N-1
|
||||
// requires rippling through N-1 XOR gates
|
||||
generate
|
||||
begin
|
||||
genvar i;
|
||||
assign b[N-1] = g[N-1];
|
||||
for (i=N-2; i >= 0; i--) begin:g2b
|
||||
assign b[i] = g[i] ^ b[i+1];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
@ -62,7 +62,7 @@ module gpio (
|
||||
// -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
|
||||
// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
if (`XLEN == 64) begin:gpio
|
||||
always_comb
|
||||
if (entryd[2]) begin
|
||||
Din = HWDATA[63:32];
|
||||
@ -71,7 +71,7 @@ module gpio (
|
||||
Din = HWDATA[31:0];
|
||||
HREADGPIO = {32'b0,Dout};
|
||||
end
|
||||
end else begin // 32-bit
|
||||
end else begin:gpio // 32-bit
|
||||
always_comb begin
|
||||
Din = HWDATA[31:0];
|
||||
HREADGPIO = Dout;
|
||||
|
||||
@ -78,7 +78,7 @@ module plic (
|
||||
// account for subword read/write circuitry
|
||||
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
if (`XLEN == 64) begin:plic
|
||||
always_comb
|
||||
if (entryd[2]) begin
|
||||
Din = HWDATA[63:32];
|
||||
@ -87,7 +87,7 @@ module plic (
|
||||
Din = HWDATA[31:0];
|
||||
HREADPLIC = {32'b0,Dout};
|
||||
end
|
||||
end else begin // 32-bit
|
||||
end else begin:plic // 32-bit
|
||||
always_comb begin
|
||||
Din = HWDATA[31:0];
|
||||
HREADPLIC = Dout;
|
||||
|
||||
@ -50,7 +50,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
|
||||
logic [3:0] busycount;
|
||||
|
||||
generate
|
||||
if(`FPGA) begin
|
||||
if(`FPGA) begin:ram
|
||||
initial begin
|
||||
//$readmemh(PRELOAD, RAM);
|
||||
// FPGA only
|
||||
@ -145,14 +145,14 @@ module ram #(parameter BASE=0, RANGE = 65535) (
|
||||
|
||||
/* verilator lint_off WIDTH */
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
if (`XLEN == 64) begin:ramrd
|
||||
always_ff @(posedge HCLK) begin
|
||||
HWADDR <= #1 A;
|
||||
HREADRam0 <= #1 RAM[A[31:3]];
|
||||
if (memwrite & risingHREADYRam) RAM[HWADDR[31:3]] <= #1 HWDATA;
|
||||
end
|
||||
end else begin
|
||||
always_ff @(posedge HCLK) begin
|
||||
always_ff @(posedge HCLK) begin:ramrd
|
||||
HWADDR <= #1 A;
|
||||
HREADRam0 <= #1 RAM[A[31:2]];
|
||||
if (memwrite & risingHREADYRam) RAM[HWADDR[31:2]] <= #1 HWDATA;
|
||||
|
||||
@ -36,7 +36,7 @@ module subwordwrite (
|
||||
logic [`XLEN-1:0] WriteDataSubwordDuplicated;
|
||||
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
if (`XLEN == 64) begin:sww
|
||||
logic [7:0] ByteMaskM;
|
||||
// Compute write mask
|
||||
always_comb
|
||||
@ -74,7 +74,7 @@ module subwordwrite (
|
||||
if (ByteMaskM[7]) HWDATA[63:56] = WriteDataSubwordDuplicated[63:56];
|
||||
end
|
||||
|
||||
end else begin // 32-bit
|
||||
end else begin:sww // 32-bit
|
||||
logic [3:0] ByteMaskM;
|
||||
// Compute write mask
|
||||
always_comb
|
||||
|
||||
@ -55,7 +55,7 @@ module uart (
|
||||
assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something
|
||||
|
||||
generate
|
||||
if (`XLEN == 64) begin
|
||||
if (`XLEN == 64) begin:uart
|
||||
always_comb begin
|
||||
HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
|
||||
case (A)
|
||||
@ -69,7 +69,7 @@ module uart (
|
||||
3'b111: Din = HWDATA[63:56];
|
||||
endcase
|
||||
end
|
||||
end else begin // 32-bit
|
||||
end else begin:uart // 32-bit
|
||||
always_comb begin
|
||||
HREADUART = {Dout, Dout, Dout, Dout};
|
||||
case (A[1:0])
|
||||
|
||||
@ -211,7 +211,7 @@ module uartPC16550D(
|
||||
if (~HRESETn) begin
|
||||
baudcount <= #1 1;
|
||||
baudpulse <= #1 0;
|
||||
end else if (~MEMWb & DLAB & (A == 3'b0 || A == 3'b1)) begin
|
||||
end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin
|
||||
baudcount <= #1 1;
|
||||
end else begin
|
||||
// the baudpulse is too long by 2 clock cycles.
|
||||
@ -248,7 +248,7 @@ module uartPC16550D(
|
||||
rxoversampledcnt <= #1 rxoversampledcnt + 1; // 16x oversampled counter
|
||||
if (rxcentered) rxbitsreceived <= #1 rxbitsreceived + 1;
|
||||
if (rxbitsreceived == rxbitsexpected) rxstate <= #1 UART_DONE; // pulse rxdone for a cycle
|
||||
end else if (rxstate == UART_DONE || rxstate == UART_BREAK) begin
|
||||
end else if (rxstate == UART_DONE | rxstate == UART_BREAK) begin
|
||||
if (rxbreak & ~SINsync) rxstate <= #1 UART_BREAK;
|
||||
else rxstate <= #1 UART_IDLE;
|
||||
end
|
||||
|
||||
@ -31,6 +31,7 @@
|
||||
module uncore (
|
||||
// AHB Bus Interface
|
||||
input logic HCLK, HRESETn,
|
||||
input logic TIMECLK,
|
||||
input logic [31:0] HADDR,
|
||||
input logic [`AHBW-1:0] HWDATAIN,
|
||||
input logic HWRITE,
|
||||
@ -59,7 +60,7 @@ module uncore (
|
||||
input logic SDCCmdIn,
|
||||
input logic [3:0] SDCDatIn,
|
||||
output logic SDCCLK,
|
||||
output logic [63:0] MTIME_CLINT, MTIMECMP_CLINT
|
||||
output logic [63:0] MTIME_CLINT
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] HWDATA;
|
||||
@ -115,16 +116,16 @@ module uncore (
|
||||
// memory-mapped I/O peripherals
|
||||
if (`CLINT_SUPPORTED == 1) begin : clint
|
||||
clint clint(
|
||||
.HCLK, .HRESETn,
|
||||
.HCLK, .HRESETn, .TIMECLK,
|
||||
.HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
|
||||
.HWDATA, .HREADY, .HTRANS,
|
||||
.HREADCLINT,
|
||||
.HRESPCLINT, .HREADYCLINT,
|
||||
.MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT),
|
||||
.MTIME(MTIME_CLINT),
|
||||
.TimerIntM, .SwIntM);
|
||||
|
||||
end else begin : clint
|
||||
assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0;
|
||||
assign MTIME_CLINT = 0;
|
||||
assign TimerIntM = 0; assign SwIntM = 0;
|
||||
end
|
||||
if (`PLIC_SUPPORTED == 1) begin : plic
|
||||
|
||||
@ -30,7 +30,7 @@ module wallypipelinedhart (
|
||||
input logic clk, reset,
|
||||
// Privileged
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
// Bus Interface
|
||||
input logic [`AHBW-1:0] HRDATA,
|
||||
input logic HREADY, HRESP,
|
||||
@ -113,7 +113,7 @@ module wallypipelinedhart (
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
|
||||
// IMem stalls
|
||||
logic ICacheStallF;
|
||||
logic IfuStallF;
|
||||
logic LSUStall;
|
||||
|
||||
|
||||
@ -128,10 +128,10 @@ module wallypipelinedhart (
|
||||
logic CommittedM;
|
||||
|
||||
// AHB ifu interface
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic [`PA_BITS-1:0] IfuBusAdr;
|
||||
logic [`XLEN-1:0] IfuBusHRDATA;
|
||||
logic IfuBusFetch;
|
||||
logic ICacheBusAck;
|
||||
logic IfuBusRead;
|
||||
logic IfuBusAck;
|
||||
|
||||
// AHB LSU interface
|
||||
logic [`PA_BITS-1:0] LsuBusAdr;
|
||||
@ -164,8 +164,8 @@ module wallypipelinedhart (
|
||||
|
||||
.ExceptionM, .PendingInterruptM,
|
||||
// Fetch
|
||||
.IfuBusHRDATA, .ICacheBusAck, .PCF, .ICacheBusAdr,
|
||||
.IfuBusFetch, .ICacheStallF,
|
||||
.IfuBusHRDATA, .IfuBusAck, .PCF, .IfuBusAdr,
|
||||
.IfuBusRead, .IfuStallF,
|
||||
|
||||
// Execute
|
||||
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
|
||||
@ -277,8 +277,8 @@ module wallypipelinedhart (
|
||||
ahblite ebu(// IFU connections
|
||||
.clk, .reset,
|
||||
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
|
||||
.ICacheBusAdr, // *** rename these to match block diagram
|
||||
.IfuBusFetch, .IfuBusHRDATA, .ICacheBusAck,
|
||||
.IfuBusAdr,
|
||||
.IfuBusRead, .IfuBusHRDATA, .IfuBusAck,
|
||||
// Signals from Data Cache
|
||||
.LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA,
|
||||
.LsuBusHRDATA,
|
||||
@ -294,7 +294,7 @@ module wallypipelinedhart (
|
||||
hazard hzu(
|
||||
.BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
|
||||
.LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD,
|
||||
.LSUStall, .ICacheStallF,
|
||||
.LSUStall, .IfuStallF,
|
||||
.FPUStallD, .FStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.EcallFaultM, .BreakpointFaultM,
|
||||
@ -323,7 +323,7 @@ module wallypipelinedhart (
|
||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
|
||||
.LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
||||
.TimerIntM, .ExtIntM, .SwIntM,
|
||||
.MTIME_CLINT, .MTIMECMP_CLINT,
|
||||
.MTIME_CLINT,
|
||||
.InstrMisalignedAdrM, .IEUAdrM,
|
||||
.SetFflagsM,
|
||||
// Trap signals from pmp/pma in mmu
|
||||
|
||||
@ -51,6 +51,7 @@ module wallypipelinedsoc (
|
||||
output logic HMASTLOCK,
|
||||
output logic HREADY,
|
||||
// I/O Interface
|
||||
input logic TIMECLK,
|
||||
input logic [31:0] GPIOPinsIn,
|
||||
output logic [31:0] GPIOPinsOut, GPIOPinsEn,
|
||||
input logic UARTSin,
|
||||
@ -67,7 +68,7 @@ module wallypipelinedsoc (
|
||||
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
|
||||
logic HRESP;
|
||||
logic TimerIntM, SwIntM; // from CLINT
|
||||
logic [63:0] MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs
|
||||
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
|
||||
logic ExtIntM; // from PLIC
|
||||
logic [2:0] HADDRD;
|
||||
logic [3:0] HSIZED;
|
||||
@ -79,16 +80,16 @@ module wallypipelinedsoc (
|
||||
// instantiate processor and memories
|
||||
wallypipelinedhart hart(.clk, .reset,
|
||||
.TimerIntM, .ExtIntM, .SwIntM,
|
||||
.MTIME_CLINT, .MTIMECMP_CLINT,
|
||||
.MTIME_CLINT,
|
||||
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
|
||||
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
|
||||
.HADDRD, .HSIZED, .HWRITED
|
||||
);
|
||||
|
||||
uncore uncore(.HCLK, .HRESETn,
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
|
||||
.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT,
|
||||
.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
|
||||
.HSELEXT,
|
||||
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK
|
||||
|
||||
|
||||
@ -50,6 +50,7 @@ module wallypipelinedsocwrapper (
|
||||
output HMASTLOCK,
|
||||
output HREADY,
|
||||
// I/O Interface
|
||||
input TIMECLK,
|
||||
input [3:0] GPIOPinsIn_IO,
|
||||
output [4:0] GPIOPinsOut_IO,
|
||||
input UARTSin,
|
||||
@ -89,32 +90,33 @@ module wallypipelinedsocwrapper (
|
||||
|
||||
// wrapper for fpga
|
||||
wallypipelinedsoc wallypipelinedsoc
|
||||
(.clk(clk),
|
||||
(.clk,
|
||||
.reset_ext(reset),
|
||||
.HRDATAEXT(HRDATAEXT),
|
||||
.HREADYEXT(HREADYEXT),
|
||||
.HRESPEXT(HRESPEXT),
|
||||
.HSELEXT(HSELEXT),
|
||||
.HCLK(HCLK),
|
||||
.HRESETn(HRESETn),
|
||||
.HADDR(HADDR),
|
||||
.HWDATA(HWDATA),
|
||||
.HWRITE(HWRITE),
|
||||
.HSIZE(HSIZE),
|
||||
.HBURST(HBURST),
|
||||
.HPROT(HPROT),
|
||||
.HTRANS(HTRANS),
|
||||
.HMASTLOCK(HMASTLOCK),
|
||||
.HREADY(HREADY),
|
||||
.GPIOPinsIn(GPIOPinsIn),
|
||||
.GPIOPinsOut(GPIOPinsOut),
|
||||
.GPIOPinsEn(GPIOPinsEn),
|
||||
.UARTSin(UARTSin),
|
||||
.UARTSout(UARTSout),
|
||||
.SDCDatIn(SDCDatIn),
|
||||
.SDCCLK(SDCCLK),
|
||||
.SDCCmdIn(SDCCmdIn),
|
||||
.SDCCmdOut(SDCCmdOut),
|
||||
.SDCCmdOE(SDCCmdOE));
|
||||
.HRDATAEXT,
|
||||
.HREADYEXT,
|
||||
.HRESPEXT,
|
||||
.HSELEXT,
|
||||
.HCLK,
|
||||
.HRESETn,
|
||||
.HADDR,
|
||||
.HWDATA,
|
||||
.HWRITE,
|
||||
.HSIZE,
|
||||
.HBURST,
|
||||
.HPROT,
|
||||
.HTRANS,
|
||||
.HMASTLOCK,
|
||||
.HREADY,
|
||||
.TIMECLK,
|
||||
.GPIOPinsIn,
|
||||
.GPIOPinsOut,
|
||||
.GPIOPinsEn,
|
||||
.UARTSin,
|
||||
.UARTSout,
|
||||
.SDCDatIn,
|
||||
.SDCCLK,
|
||||
.SDCCmdIn,
|
||||
.SDCCmdOut,
|
||||
.SDCCmdOE);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -106,17 +106,17 @@ module qsel(input logic [55:52] ps, pc,
|
||||
assign #1 magnitude = ~(&p[54:52]);
|
||||
assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52]));
|
||||
assign #1 sign = p[55] ^ cout;
|
||||
/* assign #1 magnitude = ~((ps[54]^pc[54]) && (ps[53]^pc[53]) &&
|
||||
/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
|
||||
(ps[52]^pc[52]));
|
||||
assign #1 sign = (ps[55]^pc[55])^
|
||||
(ps[54] && pc[54] || ((ps[54]^pc[54]) &&
|
||||
(ps[53]&&pc[53] || ((ps[53]^pc[53]) &&
|
||||
(ps[52]&&pc[52]))))); */
|
||||
(ps[54] & pc[54] | ((ps[54]^pc[54]) &
|
||||
(ps[53]&pc[53] | ((ps[53]^pc[53]) &
|
||||
(ps[52]&pc[52]))))); */
|
||||
|
||||
// Produce quotient = +1, 0, or -1
|
||||
assign #1 qp = magnitude && ~sign;
|
||||
assign #1 qp = magnitude & ~sign;
|
||||
assign #1 qz = ~magnitude;
|
||||
assign #1 qm = magnitude && sign;
|
||||
assign #1 qm = magnitude & sign;
|
||||
endmodule
|
||||
|
||||
//////////
|
||||
@ -243,7 +243,7 @@ module counter(input logic clk,
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (count == 54) done <= #1 1;
|
||||
else if (done || req) done <= #1 0;
|
||||
else if (done | req) done <= #1 0;
|
||||
if (req) count <= #1 0;
|
||||
else count <= #1 count+1;
|
||||
end
|
||||
|
||||
@ -28,7 +28,7 @@ module instrNameDecTB(
|
||||
10'b0000011_100: name = "LBU";
|
||||
10'b0000011_101: name = "LHU";
|
||||
10'b0000011_110: name = "LWU";
|
||||
10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
|
||||
10'b0010011_000: if (instr[31:15] == 0 & instr[11:7] ==0) name = "NOP/FLUSH";
|
||||
else name = "ADDI";
|
||||
10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
|
||||
else name = "ILLEGAL";
|
||||
@ -147,28 +147,28 @@ module instrNameDecTB(
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
|
||||
else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
|
||||
else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
|
||||
else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b1110000 & rs2 == 5'b00000) name = "FMV.X.W";
|
||||
else if (funct7 == 7'b1111000 & rs2 == 5'b00000) name = "FMV.W.X";
|
||||
else if (funct7 == 7'b1110001 & rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
|
||||
else if (funct7 == 7'b1111001 & rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMIN";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLE";
|
||||
@ -178,24 +178,24 @@ module instrNameDecTB(
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMAX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLT";
|
||||
@ -206,24 +206,24 @@ module instrNameDecTB(
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FEQ";
|
||||
else name = "ILLEGAL";
|
||||
@ -232,24 +232,24 @@ module instrNameDecTB(
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else name = "ILLEGAL";
|
||||
10'b0000111_010: name = "FLW";
|
||||
10'b0100111_010: name = "FSW";
|
||||
|
||||
@ -4,7 +4,7 @@ module logging(
|
||||
input logic [1:0] HTRANS);
|
||||
|
||||
always @(posedge clk)
|
||||
if (HTRANS != 2'b00 && HADDR == 0)
|
||||
if (HTRANS != 2'b00 & HADDR == 0)
|
||||
$display("%t Warning: access to memory address 0\n", $realtime);
|
||||
endmodule
|
||||
|
||||
|
||||
@ -387,7 +387,7 @@ module sdModel
|
||||
next_datastate = 0;
|
||||
case(dataState)
|
||||
DATA_IDLE: begin
|
||||
if ((CardStatus[12:9]==`RCV) || (mult_write == 1'b1) )
|
||||
if ((CardStatus[12:9]==`RCV) | (mult_write == 1'b1) )
|
||||
next_datastate = READ_WAITS;
|
||||
else if ((CardStatus[12:9]==`DATAS )|| (mult_read == 1'b1) )
|
||||
next_datastate = WRITE_DATA;
|
||||
|
||||
@ -74,7 +74,7 @@ module testbench();
|
||||
assign HRDATAEXT = 0;
|
||||
wallypipelinedsoc dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
logic [31:0] InstrW;
|
||||
|
||||
@ -602,7 +602,7 @@ string tests32f[] = '{
|
||||
|
||||
wallypipelinedsocwrapper dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
// Track names of instructions
|
||||
@ -661,10 +661,10 @@ string tests32f[] = '{
|
||||
always @(negedge clk)
|
||||
begin
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
if (dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
|
||||
if (dut.wallypipelinedsoc.hart.priv.EcallFaultM &
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 |
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
if (DCacheFlushDone) begin
|
||||
@ -703,9 +703,9 @@ string tests32f[] = '{
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
if (signature[i] !== ram.RAM[testadr+i] &&
|
||||
if (signature[i] !== ram.RAM[testadr+i] &
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
||||
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
// kind of hacky test for garbage right now
|
||||
errors = errors+1;
|
||||
@ -751,10 +751,10 @@ string tests32f[] = '{
|
||||
end
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
assign DCacheFlushStart = dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
|
||||
assign DCacheFlushStart = dut.wallypipelinedsoc.hart.priv.EcallFaultM &
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 |
|
||||
(dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &
|
||||
dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1));
|
||||
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
@ -779,20 +779,20 @@ endmodule
|
||||
module riscvassertions();
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float");
|
||||
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float");
|
||||
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
|
||||
assert (`ICACHE_NUMWAYS == 1 | `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`RAM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
|
||||
@ -862,7 +862,7 @@ module DCacheFlushFSM
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
|
||||
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
|
||||
@ -82,7 +82,7 @@ module testbench();
|
||||
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
|
||||
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK,
|
||||
.GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.TIMECLK(0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.UARTSin, .UARTSout,
|
||||
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
|
||||
|
||||
@ -174,7 +174,7 @@ module testbench();
|
||||
`define RF dut.hart.ieu.dp.regf.rf
|
||||
`define PC dut.hart.ifu.pcreg.q
|
||||
`define CSR_BASE dut.hart.priv.priv.csr
|
||||
`define HPMCOUNTER `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
|
||||
`define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW
|
||||
`define PMP_BASE `CSR_BASE.csrm.pmp
|
||||
`define PMPCFG genblk2.PMPCFGreg.q
|
||||
`define PMPADDR PMPADDRreg.q
|
||||
@ -183,16 +183,16 @@ module testbench();
|
||||
`define MIE `CSR_BASE.csri.MIE_REGW
|
||||
`define MIP `CSR_BASE.csri.MIP_REGW
|
||||
`define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q
|
||||
`define SCAUSE `CSR_BASE.csrs.genblk1.SCAUSEreg.q
|
||||
`define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q
|
||||
`define MEPC `CSR_BASE.csrm.MEPCreg.q
|
||||
`define SEPC `CSR_BASE.csrs.genblk1.SEPCreg.q
|
||||
`define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q
|
||||
`define MCOUNTEREN `CSR_BASE.csrm.counters.MCOUNTERENreg.q
|
||||
`define SCOUNTEREN `CSR_BASE.csrs.genblk1.genblk2.SCOUNTERENreg.q
|
||||
`define SCOUNTEREN `CSR_BASE.csrs.csrs.scounteren.SCOUNTERENreg.q
|
||||
`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
|
||||
`define SSCRATCH `CSR_BASE.csrs.genblk1.SSCRATCHreg.q
|
||||
`define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q
|
||||
`define MTVEC `CSR_BASE.csrm.MTVECreg.q
|
||||
`define STVEC `CSR_BASE.csrs.genblk1.STVECreg.q
|
||||
`define SATP `CSR_BASE.csrs.genblk1.genblk1.SATPreg.q
|
||||
`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
|
||||
`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
|
||||
`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
|
||||
`define STATUS_TSR `CSR_BASE.csrsr.STATUS_TSR_INT
|
||||
`define STATUS_TW `CSR_BASE.csrsr.STATUS_TW_INT
|
||||
@ -210,7 +210,7 @@ module testbench();
|
||||
`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
|
||||
`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
|
||||
`define PRIV dut.hart.priv.priv.privmodereg.q
|
||||
`define INSTRET dut.hart.priv.priv.csr.counters.genblk1.genblk2.INSTRETreg.q
|
||||
`define INSTRET dut.hart.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]
|
||||
// Common Macros
|
||||
`define checkCSR(CSR) \
|
||||
begin \
|
||||
@ -222,7 +222,7 @@ module testbench();
|
||||
`define checkEQ(NAME, VAL, EXPECTED) \
|
||||
if(VAL != EXPECTED) begin \
|
||||
$display("%tns, %d instrs: %s %x differs from expected %x", $time, InstrCountW, NAME, VAL, EXPECTED); \
|
||||
if ((NAME == "PCW") || (`DEBUG_TRACE >= 2)) fault = 1; \
|
||||
if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
|
||||
end
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
@ -571,13 +571,13 @@ module testbench();
|
||||
// turn on waves
|
||||
if (InstrCountW == INSTR_WAVEON) $stop;
|
||||
// end sim
|
||||
if ((InstrCountW == INSTR_LIMIT) && (INSTR_LIMIT!=0)) $stop;
|
||||
if ((InstrCountW == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop;
|
||||
fault = 0;
|
||||
if (`DEBUG_TRACE >= 1) begin
|
||||
`checkEQ("PCW",PCW,ExpectedPCW)
|
||||
//`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
|
||||
// compressed to uncompressed conversion
|
||||
`checkEQ("Instr Count",dut.hart.priv.priv.csr.counters.genblk1.INSTRET_REGW,InstrCountW)
|
||||
`checkEQ("Instr Count",dut.hart.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW)
|
||||
#2; // delay 2 ns.
|
||||
if(`DEBUG_TRACE >= 5) begin
|
||||
$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, InstrCountW, dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
|
||||
@ -612,9 +612,9 @@ module testbench();
|
||||
"mepc": `checkCSR(dut.hart.priv.priv.csr.csrm.MEPC_REGW)
|
||||
"mtval": `checkCSR(dut.hart.priv.priv.csr.csrm.MTVAL_REGW)
|
||||
"sepc": `checkCSR(dut.hart.priv.priv.csr.csrs.SEPC_REGW)
|
||||
"scause": `checkCSR(dut.hart.priv.priv.csr.csrs.genblk1.SCAUSE_REGW)
|
||||
"scause": `checkCSR(dut.hart.priv.priv.csr.csrs.csrs.SCAUSE_REGW)
|
||||
"stvec": `checkCSR(dut.hart.priv.priv.csr.csrs.STVEC_REGW)
|
||||
"stval": `checkCSR(dut.hart.priv.priv.csr.csrs.genblk1.STVAL_REGW)
|
||||
"stval": `checkCSR(dut.hart.priv.priv.csr.csrs.csrs.STVAL_REGW)
|
||||
endcase
|
||||
end
|
||||
if (fault == 1) begin
|
||||
@ -643,7 +643,7 @@ module testbench();
|
||||
// For waveview convenience
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.hart.ifu.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
@ -678,7 +678,7 @@ module testbench();
|
||||
SvMode = SATP[63];
|
||||
// Only perform translation if translation is on and the processor is not
|
||||
// in machine mode
|
||||
if (SvMode && (dut.hart.priv.priv.PrivilegeModeW != `M_MODE)) begin
|
||||
if (SvMode & (dut.hart.priv.priv.PrivilegeModeW != `M_MODE)) begin
|
||||
BaseAdr = SATP[43:0] << 12;
|
||||
for (i = 2; i >= 0; i--) begin
|
||||
PAdr = BaseAdr + (VPN[i] << 3);
|
||||
|
||||
@ -135,8 +135,8 @@ module testbench();
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
if (dut.hart.priv.EcallFaultM &
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 & dut.hart.ieu.dp.regf.a3 == 3 & dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
$display("Code ended with ecall with gp = 1");
|
||||
#60; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
|
||||
@ -152,12 +152,12 @@ logic [3:0] dummy;
|
||||
|
||||
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.hart.ifu.FinalInstrRawF,
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
@ -244,9 +244,9 @@ logic [3:0] dummy;
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
// *** have to figure out how to exclude shadowram when not using a dcache.
|
||||
if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &&
|
||||
if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
||||
if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
|
||||
// report errors unless they are garbage at the end of the sim
|
||||
// kind of hacky test for garbage right now
|
||||
errors = errors+1;
|
||||
@ -304,12 +304,12 @@ logic [3:0] dummy;
|
||||
assign ecf = 0;
|
||||
end
|
||||
endgenerate
|
||||
assign DCacheFlushStart = ecf &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1)) ||
|
||||
(dut.hart.ifu.InstrM == 32'h6f || dut.hart.ifu.InstrM == 32'hfc32a423 || dut.hart.ifu.InstrM == 32'hfc32a823) && dut.hart.ieu.c.InstrValidM;
|
||||
assign DCacheFlushStart = ecf &
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 |
|
||||
(dut.hart.ieu.dp.regf.we3 &
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &
|
||||
dut.hart.ieu.dp.regf.wd3 == 1)) |
|
||||
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
|
||||
|
||||
// **** Fix when the check in the shadow ram is fixed.
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
@ -332,26 +332,28 @@ logic [3:0] dummy;
|
||||
endmodule
|
||||
|
||||
module riscvassertions;
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
initial begin
|
||||
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`DIV_BITSPERCYCLE == 1 || `DIV_BITSPERCYCLE==2 || `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
|
||||
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
|
||||
assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support");
|
||||
assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
|
||||
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
|
||||
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS || `MEM_DCACHE==0) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS || `MEM_ICACHE==0) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS | `MEM_DCACHE==0) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS | `MEM_ICACHE==0) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
|
||||
assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported.");
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
|
||||
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -365,68 +367,74 @@ module DCacheFlushFSM
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
genvar adr;
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
generate
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.logblockbytelen(logblockbytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||
end
|
||||
if(`MEM_DCACHE) begin
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||
copyShadow #(.tagstart(tagstart),
|
||||
.logblockbytelen(logblockbytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
.CacheAdr(CacheAdr[way][index][cacheWord]),
|
||||
.CacheTag(CacheTag[way][index][cacheWord]),
|
||||
.CacheValid(CacheValid[way][index][cacheWord]),
|
||||
.CacheDirty(CacheDirty[way][index][cacheWord]));
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
integer i, j, k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
integer i, j, k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (start) begin #1
|
||||
#1
|
||||
for(i = 0; i < numlines; i++) begin
|
||||
for(j = 0; j < numways; j++) begin
|
||||
for(k = 0; k < numwords; k++) begin
|
||||
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
|
||||
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
flop #(1) doneReg(.clk(clk),
|
||||
.d(start),
|
||||
|
||||
@ -680,6 +680,7 @@ string imperas32f[] = '{
|
||||
|
||||
string imperas64i[] = '{
|
||||
`IMPERASTEST,
|
||||
"rv64i_m/I/I-DELAY_SLOTS-01", "002010",
|
||||
"rv64i_m/I/ADD-01", "004010",
|
||||
"rv64i_m/I/ADDI-01", "003010",
|
||||
"rv64i_m/I/ADDIW-01", "003010",
|
||||
@ -1046,89 +1047,89 @@ string imperas32f[] = '{
|
||||
string arch64d[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/D/d_fadd_b10-01", "8690",
|
||||
// "rv64i_m/D/d_fadd_b1-01", "8430",
|
||||
// "rv64i_m/D/d_fadd_b11-01", "74da0",
|
||||
// "rv64i_m/D/d_fadd_b12-01", "2350",
|
||||
// "rv64i_m/D/d_fadd_b13-01", "3cb0",
|
||||
// "rv64i_m/D/d_fadd_b2-01", "5160",
|
||||
// "rv64i_m/D/d_fadd_b3-01", "d640",
|
||||
// "rv64i_m/D/d_fadd_b4-01", "3900",
|
||||
// "rv64i_m/D/d_fadd_b5-01", "3d50",
|
||||
// "rv64i_m/D/d_fadd_b7-01", "5530",
|
||||
// "rv64i_m/D/d_fadd_b8-01", "11c10",
|
||||
"rv64i_m/D/d_fadd_b1-01", "8430",
|
||||
// "rv64i_m/D/d_fadd_b11-01", "74da0", //memfile
|
||||
"rv64i_m/D/d_fadd_b12-01", "2350",
|
||||
"rv64i_m/D/d_fadd_b13-01", "3cb0",
|
||||
"rv64i_m/D/d_fadd_b2-01", "5160",
|
||||
"rv64i_m/D/d_fadd_b3-01", "d640",
|
||||
"rv64i_m/D/d_fadd_b4-01", "3900",
|
||||
"rv64i_m/D/d_fadd_b5-01", "3d50",
|
||||
"rv64i_m/D/d_fadd_b7-01", "5530",
|
||||
"rv64i_m/D/d_fadd_b8-01", "11c10",
|
||||
"rv64i_m/D/d_fclass_b1-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.l_b25-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.l_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b1-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b22-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.d.l_b25-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.d.l_b26-01", "2220",
|
||||
"rv64i_m/D/d_fcvt.d.lu_b25-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.d.lu_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b1-01", "2110", // trying to put doubles into a s -> d conversion? also says 0 -/-> 0 but rather 7ff800... .signature.output looks suspicious
|
||||
// "rv64i_m/D/d_fcvt.d.s_b22-01", "2110", // ^ from here to....
|
||||
// "rv64i_m/D/d_fcvt.d.s_b23-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b24-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b27-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b28-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b29-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.w_b25-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.d.w_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b22-01", "2260",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b27-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b22-01", "2260",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b27-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b1-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b22-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b27-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b28-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.s.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b22-01", "2160",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b27-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b22-01", "2160",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b27-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b28-01", "2120",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fdiv_b1-01", "8430",
|
||||
// "rv64i_m/D/d_fdiv_b20-01", "3fa0",
|
||||
// "rv64i_m/D/d_fdiv_b2-01", "5170",
|
||||
// "rv64i_m/D/d_fdiv_b21-01", "8a70",
|
||||
// "rv64i_m/D/d_fdiv_b3-01", "d630",
|
||||
// "rv64i_m/D/d_fdiv_b4-01", "38f0",
|
||||
// "rv64i_m/D/d_fdiv_b5-01", "3d50",
|
||||
// "rv64i_m/D/d_fdiv_b6-01", "38f0",
|
||||
// "rv64i_m/D/d_fdiv_b7-01", "5530",
|
||||
// "rv64i_m/D/d_fdiv_b8-01", "11c10",
|
||||
// "rv64i_m/D/d_fdiv_b9-01", "1b0f0",
|
||||
// "rv64i_m/D/d_feq_b1-01", "7430",
|
||||
// "rv64i_m/D/d_feq_b19-01", "c4c0",
|
||||
// "rv64i_m/D/d_fld-align-01", "2010",
|
||||
// "rv64i_m/D/d_fle_b1-01", "7430",
|
||||
// "rv64i_m/D/d_fle_b19-01", "c4c0",
|
||||
// "rv64i_m/D/d_flt_b1-01", "7430",
|
||||
// "rv64i_m/D/d_flt_b19-01", "d800",
|
||||
// "rv64i_m/D/d_fcvt.d.s_b29-01", "2110", // ....here
|
||||
"rv64i_m/D/d_fcvt.d.w_b25-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.d.w_b26-01", "2220",
|
||||
"rv64i_m/D/d_fcvt.d.wu_b25-01", "2110",
|
||||
// "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220", //memfile
|
||||
"rv64i_m/D/d_fcvt.l.d_b1-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.l.d_b22-01", "2260",
|
||||
"rv64i_m/D/d_fcvt.l.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.l.d_b24-01", "2360", // memfile
|
||||
"rv64i_m/D/d_fcvt.l.d_b27-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.l.d_b28-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.l.d_b29-01", "22a0",
|
||||
"rv64i_m/D/d_fcvt.lu.d_b1-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.lu.d_b22-01", "2260",
|
||||
"rv64i_m/D/d_fcvt.lu.d_b23-01", "2180",
|
||||
"rv64i_m/D/d_fcvt.lu.d_b24-01", "2360",
|
||||
"rv64i_m/D/d_fcvt.lu.d_b27-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.lu.d_b28-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0",
|
||||
"rv64i_m/D/d_fcvt.s.d_b1-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.s.d_b22-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.s.d_b23-01", "2180",
|
||||
"rv64i_m/D/d_fcvt.s.d_b24-01", "2360",
|
||||
"rv64i_m/D/d_fcvt.s.d_b27-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.s.d_b28-01", "2110",
|
||||
"rv64i_m/D/d_fcvt.s.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.w.d_b1-01", "2120", // memfile
|
||||
// "rv64i_m/D/d_fcvt.w.d_b22-01", "2160", // memfile
|
||||
"rv64i_m/D/d_fcvt.w.d_b23-01", "2180",
|
||||
"rv64i_m/D/d_fcvt.w.d_b24-01", "2360",
|
||||
"rv64i_m/D/d_fcvt.w.d_b27-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.w.d_b28-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.w.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120", // memfile
|
||||
"rv64i_m/D/d_fcvt.wu.d_b22-01", "2160",
|
||||
"rv64i_m/D/d_fcvt.wu.d_b23-01", "2180",
|
||||
// "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360", // memfile
|
||||
"rv64i_m/D/d_fcvt.wu.d_b27-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.wu.d_b28-01", "2120",
|
||||
"rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0",
|
||||
// "rv64i_m/D/d_fdiv_b1-01", "8430", // RV NaNs need to be positive
|
||||
// "rv64i_m/D/d_fdiv_b20-01", "3fa0", // looks like flags
|
||||
// "rv64i_m/D/d_fdiv_b2-01", "5170", // also flags
|
||||
// "rv64i_m/D/d_fdiv_b21-01", "8a70", // positive NaNs again
|
||||
"rv64i_m/D/d_fdiv_b3-01", "d630",
|
||||
// "rv64i_m/D/d_fdiv_b4-01", "38f0", // flags
|
||||
"rv64i_m/D/d_fdiv_b5-01", "3d50",
|
||||
// "rv64i_m/D/d_fdiv_b6-01", "38f0", // flags
|
||||
"rv64i_m/D/d_fdiv_b7-01", "5530",
|
||||
// "rv64i_m/D/d_fdiv_b8-01", "11c10", // flags
|
||||
// "rv64i_m/D/d_fdiv_b9-01", "1b0f0", // memfile might be a flag too
|
||||
"rv64i_m/D/d_feq_b1-01", "7430",
|
||||
"rv64i_m/D/d_feq_b19-01", "c4c0",
|
||||
"rv64i_m/D/d_fld-align-01", "2010",
|
||||
"rv64i_m/D/d_fle_b1-01", "7430",
|
||||
"rv64i_m/D/d_fle_b19-01", "c4c0",
|
||||
"rv64i_m/D/d_flt_b1-01", "7430",
|
||||
"rv64i_m/D/d_flt_b19-01", "d800",
|
||||
"rv64i_m/D/d_fmadd_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fmadd_b16-01", "43b0",
|
||||
"rv64i_m/D/d_fmadd_b17-01", "43b0",
|
||||
"rv64i_m/D/d_fmadd_b18-01", "5a20",
|
||||
// "rv64i_m/D/d_fmadd_b17-01", "43b0", //memfile
|
||||
// "rv64i_m/D/d_fmadd_b18-01", "5a20", // memfile
|
||||
"rv64i_m/D/d_fmadd_b2-01", "5ab0",
|
||||
"rv64i_m/D/d_fmadd_b3-01", "119d0",
|
||||
"rv64i_m/D/d_fmadd_b4-01", "3df0",
|
||||
@ -1141,9 +1142,9 @@ string imperas32f[] = '{
|
||||
"rv64i_m/D/d_fmin_b1-01", "8430",
|
||||
"rv64i_m/D/d_fmin_b19-01", "d4b0",
|
||||
"rv64i_m/D/d_fmsub_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fmsub_b16-01", "43b0",
|
||||
"rv64i_m/D/d_fmsub_b17-01", "43b0",
|
||||
"rv64i_m/D/d_fmsub_b18-01", "5a20",
|
||||
// "rv64i_m/D/d_fmsub_b16-01", "43b0", // memfile
|
||||
// "rv64i_m/D/d_fmsub_b17-01", "43b0",
|
||||
// "rv64i_m/D/d_fmsub_b18-01", "5a20", // memfile
|
||||
"rv64i_m/D/d_fmsub_b2-01", "5ab0",
|
||||
"rv64i_m/D/d_fmsub_b3-01", "119f0",
|
||||
"rv64i_m/D/d_fmsub_b4-01", "3df0",
|
||||
@ -1172,9 +1173,9 @@ string imperas32f[] = '{
|
||||
"rv64i_m/D/d_fnmadd_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fnmadd_b16-01", "4390",
|
||||
"rv64i_m/D/d_fnmadd_b17-01", "4390",
|
||||
"rv64i_m/D/d_fnmadd_b18-01", "5a20",
|
||||
// "rv64i_m/D/d_fnmadd_b18-01", "5a20", // memfile
|
||||
"rv64i_m/D/d_fnmadd_b2-01", "5ab0",
|
||||
"rv64i_m/D/d_fnmadd_b3-01", "119d0",
|
||||
// "rv64i_m/D/d_fnmadd_b3-01", "119d0", // memfile
|
||||
"rv64i_m/D/d_fnmadd_b4-01", "3df0",
|
||||
"rv64i_m/D/d_fnmadd_b5-01", "4480",
|
||||
"rv64i_m/D/d_fnmadd_b6-01", "3df0",
|
||||
@ -1182,28 +1183,28 @@ string imperas32f[] = '{
|
||||
"rv64i_m/D/d_fnmadd_b8-01", "15aa0",
|
||||
"rv64i_m/D/d_fnmsub_b14-01", "3fd0",
|
||||
"rv64i_m/D/d_fnmsub_b16-01", "4390",
|
||||
"rv64i_m/D/d_fnmsub_b17-01", "4390",
|
||||
"rv64i_m/D/d_fnmsub_b18-01", "5a20",
|
||||
// "rv64i_m/D/d_fnmsub_b17-01", "4390", // memfile - there's a "it" in the file
|
||||
// "rv64i_m/D/d_fnmsub_b18-01", "5a20", // memfile
|
||||
"rv64i_m/D/d_fnmsub_b2-01", "5aa0",
|
||||
"rv64i_m/D/d_fnmsub_b3-01", "119d0",
|
||||
"rv64i_m/D/d_fnmsub_b4-01", "3e20",
|
||||
"rv64i_m/D/d_fnmsub_b5-01", "4480",
|
||||
"rv64i_m/D/d_fnmsub_b6-01", "3e10",
|
||||
"rv64i_m/D/d_fnmsub_b7-01", "6050",
|
||||
"rv64i_m/D/d_fnmsub_b8-01", "15aa0",
|
||||
// "rv64i_m/D/d_fnmsub_b8-01", "15aa0", // memfile - not obvious have to check with .elf.debug
|
||||
"rv64i_m/D/d_fsd-align-01", "2010",
|
||||
"rv64i_m/D/d_fsgnj_b1-01", "8430",
|
||||
"rv64i_m/D/d_fsgnjn_b1-01", "8430",
|
||||
"rv64i_m/D/d_fsgnjx_b1-01", "8430",
|
||||
"rv64i_m/D/d_fsqrt_b1-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b20-01", "3460",
|
||||
"rv64i_m/D/d_fsqrt_b2-01", "2190",
|
||||
"rv64i_m/D/d_fsqrt_b3-01", "2120",
|
||||
"rv64i_m/D/d_fsqrt_b4-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b5-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b7-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b8-01", "2110",
|
||||
"rv64i_m/D/d_fsqrt_b9-01", "4c10",
|
||||
// "rv64i_m/D/d_fsqrt_b1-01", "2110", // flg
|
||||
// "rv64i_m/D/d_fsqrt_b20-01", "3460", // flg
|
||||
// "rv64i_m/D/d_fsqrt_b2-01", "2190", // flg - I'm going to stop here with the sqrt
|
||||
// "rv64i_m/D/d_fsqrt_b3-01", "2120",
|
||||
// "rv64i_m/D/d_fsqrt_b4-01", "2110",
|
||||
// "rv64i_m/D/d_fsqrt_b5-01", "2110",
|
||||
// "rv64i_m/D/d_fsqrt_b7-01", "2110",
|
||||
// "rv64i_m/D/d_fsqrt_b8-01", "2110",
|
||||
// "rv64i_m/D/d_fsqrt_b9-01", "4c10",
|
||||
"rv64i_m/D/d_fsub_b10-01", "8660",
|
||||
"rv64i_m/D/d_fsub_b1-01", "8440",
|
||||
"rv64i_m/D/d_fsub_b11-01", "74da0",
|
||||
@ -1251,37 +1252,37 @@ string imperas32f[] = '{
|
||||
|
||||
string arch32f[] = '{
|
||||
`RISCVARCHTEST,
|
||||
// "rv32i_m/F/fadd_b1-01", "7220",
|
||||
// "rv32i_m/F/fadd_b10-01", "2270",
|
||||
// "rv32i_m/F/fadd_b11-01", "3fb40",
|
||||
// "rv32i_m/F/fadd_b12-01", "21b0",
|
||||
// "rv32i_m/F/fadd_b13-01", "3660",
|
||||
// "rv32i_m/F/fadd_b2-01", "38b0",
|
||||
// "rv32i_m/F/fadd_b3-01", "b320",
|
||||
// "rv32i_m/F/fadd_b4-01", "3480",
|
||||
// "rv32i_m/F/fadd_b5-01", "3700",
|
||||
// "rv32i_m/F/fadd_b7-01", "3520",
|
||||
// "rv32i_m/F/fadd_b8-01", "104a0",
|
||||
"rv32i_m/F/fadd_b1-01", "7220",
|
||||
"rv32i_m/F/fadd_b10-01", "2270",
|
||||
"rv32i_m/F/fadd_b11-01", "3fb40",
|
||||
"rv32i_m/F/fadd_b12-01", "21b0",
|
||||
"rv32i_m/F/fadd_b13-01", "3660",
|
||||
"rv32i_m/F/fadd_b2-01", "38b0",
|
||||
"rv32i_m/F/fadd_b3-01", "b320",
|
||||
"rv32i_m/F/fadd_b4-01", "3480",
|
||||
"rv32i_m/F/fadd_b5-01", "3700",
|
||||
"rv32i_m/F/fadd_b7-01", "3520",
|
||||
"rv32i_m/F/fadd_b8-01", "104a0",
|
||||
"rv32i_m/F/fclass_b1-01", "2090",
|
||||
"rv32i_m/F/fcvt.s.w_b25-01", "20a0",
|
||||
"rv32i_m/F/fcvt.s.w_b26-01", "3290",
|
||||
"rv32i_m/F/fcvt.s.wu_b25-01", "20a0",
|
||||
"rv32i_m/F/fcvt.s.wu_b26-01", "3290",
|
||||
// "rv32i_m/F/fcvt.w.s_b1-01", "2090",
|
||||
// "rv32i_m/F/fcvt.w.s_b22-01", "20b0",
|
||||
// "rv32i_m/F/fcvt.w.s_b23-01", "20c0",
|
||||
// "rv32i_m/F/fcvt.w.s_b24-01", "21b0",
|
||||
// "rv32i_m/F/fcvt.w.s_b27-01", "2090",
|
||||
// "rv32i_m/F/fcvt.w.s_b28-01", "2090",
|
||||
// "rv32i_m/F/fcvt.w.s_b29-01", "2150",
|
||||
// "rv32i_m/F/fcvt.wu.s_b1-01", "2090",
|
||||
// "rv32i_m/F/fcvt.wu.s_b22-01", "20b0",
|
||||
// "rv32i_m/F/fcvt.wu.s_b23-01", "20c0",
|
||||
// "rv32i_m/F/fcvt.wu.s_b24-01", "21b0",
|
||||
// "rv32i_m/F/fcvt.wu.s_b27-01", "2090",
|
||||
// "rv32i_m/F/fcvt.wu.s_b28-01", "2090",
|
||||
// "rv32i_m/F/fcvt.wu.s_b29-01", "2150",
|
||||
// "rv32i_m/F/fdiv_b1-01", "7220",
|
||||
"rv32i_m/F/fcvt.w.s_b1-01", "2090",
|
||||
"rv32i_m/F/fcvt.w.s_b22-01", "20b0",
|
||||
"rv32i_m/F/fcvt.w.s_b23-01", "20c0",
|
||||
"rv32i_m/F/fcvt.w.s_b24-01", "21b0",
|
||||
"rv32i_m/F/fcvt.w.s_b27-01", "2090",
|
||||
"rv32i_m/F/fcvt.w.s_b28-01", "2090",
|
||||
"rv32i_m/F/fcvt.w.s_b29-01", "2150",
|
||||
"rv32i_m/F/fcvt.wu.s_b1-01", "2090",
|
||||
"rv32i_m/F/fcvt.wu.s_b22-01", "20b0",
|
||||
"rv32i_m/F/fcvt.wu.s_b23-01", "20c0",
|
||||
"rv32i_m/F/fcvt.wu.s_b24-01", "21b0",
|
||||
"rv32i_m/F/fcvt.wu.s_b27-01", "2090",
|
||||
"rv32i_m/F/fcvt.wu.s_b28-01", "2090",
|
||||
"rv32i_m/F/fcvt.wu.s_b29-01", "2150",
|
||||
// "rv32i_m/F/fdiv_b1-01", "7220", // NaN i'm going to skip div, probably the same problems as the double version
|
||||
// "rv32i_m/F/fdiv_b2-01", "2350",
|
||||
// "rv32i_m/F/fdiv_b20-01", "38c0",
|
||||
// "rv32i_m/F/fdiv_b21-01", "7540",
|
||||
@ -1292,41 +1293,41 @@ string imperas32f[] = '{
|
||||
// "rv32i_m/F/fdiv_b7-01", "3520",
|
||||
// "rv32i_m/F/fdiv_b8-01", "104a0",
|
||||
// "rv32i_m/F/fdiv_b9-01", "d960",
|
||||
// "rv32i_m/F/feq_b1-01", "6220",
|
||||
// "rv32i_m/F/feq_b19-01", "a190",
|
||||
// "rv32i_m/F/fle_b1-01", "6220",
|
||||
// "rv32i_m/F/fle_b19-01", "a190",
|
||||
// "rv32i_m/F/flt_b1-01", "6220",
|
||||
// "rv32i_m/F/flt_b19-01", "8ee0",
|
||||
"rv32i_m/F/feq_b1-01", "6220",
|
||||
"rv32i_m/F/feq_b19-01", "a190",
|
||||
"rv32i_m/F/fle_b1-01", "6220",
|
||||
// "rv32i_m/F/fle_b19-01", "a190", // looks fine to me is the actual input value supposed to be infinity?
|
||||
"rv32i_m/F/flt_b1-01", "6220",
|
||||
// "rv32i_m/F/flt_b19-01", "8ee0", // memfile
|
||||
"rv32i_m/F/flw-align-01", "2010",
|
||||
"rv32i_m/F/fmadd_b1-01", "96860",
|
||||
"rv32i_m/F/fmadd_b14-01", "23d0",
|
||||
//--passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", "19bb30",
|
||||
// --passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", "19bb30",
|
||||
"rv32i_m/F/fmadd_b16-01", "39d0",
|
||||
"rv32i_m/F/fmadd_b17-01", "39d0",
|
||||
"rv32i_m/F/fmadd_b18-01", "4d10",
|
||||
// "rv32i_m/F/fmadd_b18-01", "4d10", // memfile - incorrect last value - ln 4931 supposed to be 71bffff8
|
||||
"rv32i_m/F/fmadd_b2-01", "4d60",
|
||||
"rv32i_m/F/fmadd_b3-01", "d4f0",
|
||||
"rv32i_m/F/fmadd_b4-01", "3700",
|
||||
"rv32i_m/F/fmadd_b5-01", "3ac0",
|
||||
"rv32i_m/F/fmadd_b6-01", "3700",
|
||||
// "rv32i_m/F/fmadd_b7-01", "d7f0",
|
||||
// "rv32i_m/F/fmadd_b8-01", "13f30",
|
||||
// "rv32i_m/F/fmax_b1-01", "7220",
|
||||
// "rv32i_m/F/fmax_b19-01", "9e00",
|
||||
// "rv32i_m/F/fmin_b1-01", "7220",
|
||||
// "rv32i_m/F/fmin_b19-01", "9f20",
|
||||
// "rv32i_m/F/fmadd_b7-01", "d7f0", // input values aren't even in the memfile are being used in the test
|
||||
// "rv32i_m/F/fmadd_b8-01", "13f30", // memfile incorrect input - last test input Z
|
||||
"rv32i_m/F/fmax_b1-01", "7220",
|
||||
"rv32i_m/F/fmax_b19-01", "9e00",
|
||||
"rv32i_m/F/fmin_b1-01", "7220",
|
||||
"rv32i_m/F/fmin_b19-01", "9f20",
|
||||
"rv32i_m/F/fmsub_b1-01", "96860",
|
||||
"rv32i_m/F/fmsub_b14-01", "23d0",
|
||||
// "rv32i_m/F/fmsub_b15-01", "19bb30",
|
||||
"rv32i_m/F/fmsub_b15-01", "19bb30",
|
||||
"rv32i_m/F/fmsub_b16-01", "39d0",
|
||||
"rv32i_m/F/fmsub_b17-01", "39d0",
|
||||
"rv32i_m/F/fmsub_b18-01", "42d0",
|
||||
// "rv32i_m/F/fmsub_b18-01", "42d0", // test looks fine to me: 7e9db2ee (large number) * -0 - f1bffff8 = f1bffff8 but wants 7f800000 (NaN)
|
||||
"rv32i_m/F/fmsub_b2-01", "4d60",
|
||||
"rv32i_m/F/fmsub_b3-01", "d4f0",
|
||||
"rv32i_m/F/fmsub_b4-01", "3700",
|
||||
"rv32i_m/F/fmsub_b5-01", "3ac0",
|
||||
"rv32i_m/F/fmsub_b6-01", "3700",
|
||||
// "rv32i_m/F/fmsub_b6-01", "3700", // memfile
|
||||
"rv32i_m/F/fmsub_b7-01", "37f0",
|
||||
"rv32i_m/F/fmsub_b8-01", "13f30",
|
||||
"rv32i_m/F/fmul_b1-01", "7220",
|
||||
@ -1334,7 +1335,7 @@ string imperas32f[] = '{
|
||||
"rv32i_m/F/fmul_b3-01", "b320",
|
||||
"rv32i_m/F/fmul_b4-01", "3480",
|
||||
"rv32i_m/F/fmul_b5-01", "3700",
|
||||
"rv32i_m/F/fmul_b6-01", "3480",
|
||||
// "rv32i_m/F/fmul_b6-01", "3480", // memfile
|
||||
"rv32i_m/F/fmul_b7-01", "3520",
|
||||
"rv32i_m/F/fmul_b8-01", "104a0",
|
||||
"rv32i_m/F/fmul_b9-01", "d960",
|
||||
@ -1352,7 +1353,7 @@ string imperas32f[] = '{
|
||||
// timeconsuming "rv32i_m/F/fnmadd_b15-01", "19bb40",
|
||||
"rv32i_m/F/fnmadd_b16-01", "39d0",
|
||||
"rv32i_m/F/fnmadd_b17-01", "39d0",
|
||||
"rv32i_m/F/fnmadd_b18-01", "4d10",
|
||||
// "rv32i_m/F/fnmadd_b18-01", "4d10", // memfile
|
||||
"rv32i_m/F/fnmadd_b2-01", "4d60",
|
||||
"rv32i_m/F/fnmadd_b3-01", "d4f0",
|
||||
"rv32i_m/F/fnmadd_b4-01", "3700",
|
||||
@ -1361,30 +1362,30 @@ string imperas32f[] = '{
|
||||
"rv32i_m/F/fnmadd_b7-01", "37f0",
|
||||
"rv32i_m/F/fnmadd_b8-01", "13f30",
|
||||
"rv32i_m/F/fnmsub_b1-01", "96870",
|
||||
"rv32i_m/F/fnmsub_b14-01", "23d0",
|
||||
// "rv32i_m/F/fnmsub_b14-01", "23d0", // memfile
|
||||
// timeconsuming "rv32i_m/F/fnmsub_b15-01", "19bb30",
|
||||
"rv32i_m/F/fnmsub_b16-01", "39d0",
|
||||
"rv32i_m/F/fnmsub_b17-01", "39d0",
|
||||
"rv32i_m/F/fnmsub_b18-01", "4d10",
|
||||
// "rv32i_m/F/fnmsub_b18-01", "4d10", // memfile
|
||||
"rv32i_m/F/fnmsub_b2-01", "4d60",
|
||||
"rv32i_m/F/fnmsub_b3-01", "4df0",
|
||||
// "rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile
|
||||
"rv32i_m/F/fnmsub_b4-01", "3700",
|
||||
"rv32i_m/F/fnmsub_b5-01", "3ac0",
|
||||
"rv32i_m/F/fnmsub_b6-01", "3700",
|
||||
"rv32i_m/F/fnmsub_b7-01", "37f0",
|
||||
// "rv32i_m/F/fnmsub_b7-01", "37f0", // memfile last input merged with a deadbeef
|
||||
"rv32i_m/F/fnmsub_b8-01", "13f30",
|
||||
"rv32i_m/F/fsgnj_b1-01", "7220",
|
||||
"rv32i_m/F/fsgnjn_b1-01", "7220",
|
||||
"rv32i_m/F/fsgnjx_b1-01", "7220",
|
||||
"rv32i_m/F/fsqrt_b1-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b2-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b20-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b3-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b4-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b5-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b7-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b8-01", "2090",
|
||||
"rv32i_m/F/fsqrt_b9-01", "3310",
|
||||
// "rv32i_m/F/fsqrt_b1-01", "2090", // flag i am skiping sqrt
|
||||
// "rv32i_m/F/fsqrt_b2-01", "2090",
|
||||
// "rv32i_m/F/fsqrt_b20-01", "2090",
|
||||
// "rv32i_m/F/fsqrt_b3-01", "2090",
|
||||
// "rv32i_m/F/fsqrt_b4-01", "2090",
|
||||
// "rv32i_m/F/fsqrt_b5-01", "2090",
|
||||
// "rv32i_m/F/fsqrt_b7-01", "2090",
|
||||
// "rv32i_m/F/fsqrt_b8-01", "2090",
|
||||
// "rv32i_m/F/fsqrt_b9-01", "3310",
|
||||
"rv32i_m/F/fsub_b1-01", "7220",
|
||||
"rv32i_m/F/fsub_b10-01", "2250",
|
||||
"rv32i_m/F/fsub_b11-01", "3fb40",
|
||||
@ -1394,7 +1395,7 @@ string imperas32f[] = '{
|
||||
"rv32i_m/F/fsub_b3-01", "b320",
|
||||
"rv32i_m/F/fsub_b4-01", "3480",
|
||||
"rv32i_m/F/fsub_b5-01", "3700",
|
||||
"rv32i_m/F/fsub_b7-01", "3520",
|
||||
// "rv32i_m/F/fsub_b7-01", "3520", // memfile
|
||||
"rv32i_m/F/fsub_b8-01", "104a0",
|
||||
"rv32i_m/F/fsw-align-01", "2010"
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user