Commit Graph

8517 Commits

Author SHA1 Message Date
David Harris
5d97858806 Moved functional coverage files to sim/questa and to tests/riscvdv 2024-04-24 11:46:38 -07:00
David Harris
160c11d786 Integrating riscv-dv coverage 2024-04-24 10:17:49 -07:00
David Harris
eb7e5d4bc2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-04-24 09:47:56 -07:00
David Harris
5f3676dfd7
Merge pull request #753 from quswarabid/riscvdv_bringup
RISCVDV bringup - Coverage Collection on RISCVISACOV
2024-04-24 09:47:34 -07:00
David Harris
d11de0f28a Added nobpred case to nightly regression 2024-04-24 08:46:06 -07:00
David Harris
e52409e916 Hard-coded NUM_THREADS in tool-chain-install to make it easier to paste code 2024-04-24 08:45:07 -07:00
David Harris
235a3dcfca ROM preload compatible with Verilator lint, sim, and Design Compiler 2024-04-24 08:44:37 -07:00
David Harris
3950588b8c Brought subrepos up to date 2024-04-24 07:36:42 -07:00
Rose Thompson
195d9539bb
Merge pull request #747 from davidharrishmc/dev
Zcb tests & other cleanup
2024-04-24 08:45:31 -05:00
David Harris
32b6e6a8ab fround progress 2024-04-24 04:42:47 -07:00
David Harris
e2894ed278 derived nobpred_rv32gc config for coremark test 2024-04-24 04:41:25 -07:00
Quswar Abid
f45efea9c9 Bringup of RISCV-DV to collect functional coverage - ADDED the Make flow to run a regression of tests (RV64GC) from RISCV-DV on seed 0 and collect functional coverage 2024-04-23 18:23:34 -07:00
Quswar Abid
c0a0c1e9e5 Bringup of RISCV-DV to collect functional coverage - sample the .bashrc file to export environmental variables that RISCV-DV uses 2024-04-23 18:21:54 -07:00
Quswar Abid
7b441d2881 Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV 2024-04-23 18:20:29 -07:00
David Harris
a722c7cd08 Ignoring vcd output 2024-04-23 10:19:53 -07:00
David Harris
0dc2c7d16a Fixed deriv path in Verilator makefile 2024-04-23 10:19:08 -07:00
David Harris
2dd54b3612 adding ssmtp for nightly regression emails 2024-04-23 10:18:28 -07:00
David Harris
2f5680b7a6 Silencing new version of Verilator in lint 2024-04-23 10:18:00 -07:00
David Harris
6415bfc3c2 Code and testbench cleanup 2024-04-23 10:17:44 -07:00
David Harris
f9eec8c43f Merged wsim changes 2024-04-22 13:11:35 -07:00
David Harris
7586ecd317
Merge pull request #751 from Karl-Han/vcd
Add support for dumping vcd.
2024-04-22 13:09:58 -07:00
Kunlin Han
9be0303493 Add support for dumping vcd. 2024-04-22 13:03:51 -07:00
David Harris
bd1afa53f8 simulation cleanup 2024-04-22 12:28:16 -07:00
David Harris
cc236bdb25 Resolved merge conflicts 2024-04-22 12:16:06 -07:00
David Harris
750fb6bfce
Merge pull request #750 from Karl-Han/verilator
Run verilator configurations and testsuites in different folders.
2024-04-22 11:36:32 -07:00
Kunlin Han
c134b712c4
Merge branch 'main' into verilator 2024-04-22 11:35:18 -07:00
Kunlin Han
c383bef1ad Run verilator configurations and testsuites in different folders. 2024-04-22 11:32:46 -07:00
David Harris
76367822bf
Merge pull request #749 from Karl-Han/docker
Replace spaces of Makefile and Add some helper targets
2024-04-22 11:09:12 -07:00
Kunlin Han
d4fa95910a Add some helper targets. 2024-04-22 10:49:02 -07:00
David Harris
7944459fc9
Merge pull request #748 from ross144/main
FPGA fixex required after regress updates and added compatiblity for cygwin.
2024-04-22 08:53:50 -07:00
Rose Thompson
8123695831 Maded insert_debug_comment.sh compatible with cygwin. 2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301 Fixed fpga to work with the updated regression changes. 2024-04-22 10:42:01 -05:00
David Harris
26711083df Flushing uart.out file to observe progress 2024-04-21 20:08:35 -07:00
David Harris
45196a9959 ignore VCS junk files 2024-04-21 19:49:55 -07:00
David Harris
03f49dea3f regression printing improvements 2024-04-21 19:45:09 -07:00
David Harris
3f195884e9 Defined bit sizes more precisely to help VCS lint and conform to coding style 2024-04-21 08:40:11 -07:00
David Harris
1759c920bb improved regression comments 2024-04-21 08:38:59 -07:00
David Harris
be15a11622 Fixed conflicts on getenv 2024-04-21 08:38:13 -07:00
David Harris
0419b5484a parameterized register names in peripherals 2024-04-21 07:43:01 -07:00
David Harris
00a1c0fc57 Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors 2024-04-21 00:02:15 -07:00
David Harris
1817ab2e11 testbench import is happy now for Questa, but throws lint warning for VCS 2024-04-20 23:13:13 -07:00
David Harris
fd6a6b2249 environment variable cleanup 2024-04-20 22:52:08 -07:00
David Harris
f39e240082 Spacing cleanup 2024-04-20 20:53:49 -07:00
David Harris
25a26656b6 Removed unnecessary ZBB from BMU extract mux 2024-04-20 20:53:14 -07:00
David Harris
a1876b1e7c script cleanup 2024-04-20 17:22:31 -07:00
David Harris
338f37b570 Moved getenv/getenvval declaration to config-shared so lint and regression both run 2024-04-20 17:19:42 -07:00
David Harris
571b67f565 Merging PR738 2024-04-20 17:15:17 -07:00
David Harris
e467e46967
Merge pull request #738 from slmnemo/linux_nightly
Added full Linux boot to regression-wally
2024-04-20 17:08:43 -07:00
slmnemo
f0229e970b Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench. 2024-04-20 17:07:54 -07:00
slmnemo
66a002d879 Removed unused rmCmd string declaration 2024-04-20 16:58:23 -07:00