Ross Thompson
5281077531
More progress towards cmo.
2023-08-15 18:17:15 -05:00
Ross Thompson
9f37fef145
The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
2023-08-14 16:39:18 -05:00
Ross Thompson
0eac74ac7b
Initial CMO implementation. Just adds control signals into the L1 caches.
2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7
Cache cleanup.
2023-07-31 14:12:53 -05:00
Ross Thompson
faaf43fa10
Merge pull request #372 from davidharrishmc/dev
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PLIC part select warnings fixed
2023-07-31 11:28:28 -04:00
David Harris
6ff2b0cc2c
Merge pull request #373 from harshinisrinath1001/main
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Improved testing of pmd in priv, fixed bugs, and attempted to reset menvcfg and fixed spacing in fpu/fma and fpu/postprocessing
2023-07-30 22:46:44 -07:00
Harshini Srinath
7ed4cf97ed
Fixed formatting
2023-07-30 18:36:25 -07:00
Harshini Srinath
603ed2160e
Fixed formatting
2023-07-30 18:30:23 -07:00
Harshini Srinath
acbbe7941a
Fixed formatting
2023-07-30 18:27:22 -07:00
Harshini Srinath
e4de9ae87c
Fixed formatting
2023-07-30 18:18:24 -07:00
Harshini Srinath
4c1a07eb9c
Fixed formatting
2023-07-30 18:06:25 -07:00
Harshini Srinath
1badc8a8c5
Fixed formatting
2023-07-30 18:00:39 -07:00
Harshini Srinath
41555b149e
Fixed formatting
2023-07-30 17:54:47 -07:00
Harshini Srinath
8e97224cd7
Fixed formatting
2023-07-30 17:46:23 -07:00
Harshini Srinath
469b03577d
Fixed formatting
2023-07-30 17:39:37 -07:00
Harshini Srinath
141384f60f
Fixed formatting
2023-07-30 17:38:22 -07:00
Harshini Srinath
bbbd5f6b2d
Fixed spacing
2023-07-30 17:32:46 -07:00
Harshini Srinath
d7b2d84124
Fixed spacing
2023-07-30 17:22:40 -07:00
Harshini Srinath
b129068a92
Fixed spacing
2023-07-30 17:21:52 -07:00
Harshini Srinath
49823ccd45
Fixed spacing
2023-07-30 17:21:22 -07:00
Harshini Srinath
36108e4b52
Fixed spacing
2023-07-30 17:18:25 -07:00
Harshini Srinath
d88b2fd9c1
Fixed spacing
2023-07-30 16:59:27 -07:00
Harshini Srinath
d69d0ececc
Fixed spacing
2023-07-30 16:57:57 -07:00
David Harris
d58ece3d44
renamed test-shared.vh to config-shared.vh
2023-07-30 05:22:39 -07:00
David Harris
28823aca6e
Cleaned up lint for plic_apb part select
2023-07-30 02:00:38 -07:00
David Harris
654cafb7f7
Fixed Questa warnings in plic_apb about part select out of bounds
2023-07-30 01:54:41 -07:00
Ross Thompson
7e06775135
Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
2023-07-28 11:20:29 -05:00
Ross Thompson
15dc76310e
Fixed lint errors for issue #368 . Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN.
2023-07-26 15:08:01 -05:00
Ross Thompson
2dac02c14c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-07-25 15:13:07 -05:00
David Harris
ca62487e4c
Formatting cleanup
2023-07-25 05:11:38 -07:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
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Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
63afd95ad3
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
f895898d22
Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.
2023-07-21 16:31:26 -05:00
Ross Thompson
d04d2afed2
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
c0966c32e5
Improved critical path.
2023-07-19 14:59:37 -05:00
Ross Thompson
538efaf771
Optimized critial path in ifu's spill logic.
2023-07-19 14:13:46 -05:00
Ross Thompson
af0e33209f
Removed QEMU from configurations.
2023-07-19 10:23:55 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
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The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
42e6364b3d
Merge branch 'main' of github.com:ross144/cvw
2023-07-17 15:52:27 -05:00
Ross Thompson
c82638774f
Updated the FPGA zero stage bootloader.
2023-07-17 15:52:13 -05:00
Ross Thompson
50bc679fef
Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.
2023-07-14 16:31:44 -05:00
Jacob Pease
b3aaa87cba
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
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Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
David Harris
644afa16cd
Clean up privilege rs1 decoding and implement svinval as sfence.vma
2023-07-13 02:41:17 -07:00
Ross Thompson
625192d9a4
Merge branch 'main' of github.com:ross144/cvw into main
2023-07-11 15:08:26 -05:00
Ross Thompson
38f32805ae
Created separate temporary testbench for xcelium.
2023-07-11 15:07:33 -05:00
Ross Thompson
4c4eb080ee
RTL changes for Xcelium.
2023-07-11 10:51:02 -05:00
Ross Thompson
12beada55b
Fixed the privilege decoder bug which prevented the fpga linux boot.
2023-07-10 17:00:06 -05:00
Ross Thompson
beaec570c7
Merge pull request #359 from davidharrishmc/dev
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CSR updates
2023-07-10 13:16:57 -04:00
