Ross Thompson
b8572d6a2a
Changed several things.
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Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Ross Thompson
2f4ee26b60
Fixed issue with dtim (fpga) external abhlite select not triggering.
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Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
Ross Thompson
f7583d0e0d
Updated uncore to use sdc.
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Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
77a89c30de
Fixed bug with the external memory region selection.
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Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
James E. Stine
eb64a7f0c9
Update to fpdivsqrt to go on posedge as it should. Also an update to
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individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
886a650da4
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
3d9d4cc03f
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
a8ce4568aa
Divider FSM simplification
2021-10-10 22:24:14 -07:00
David Harris
a077735ecc
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
bbracker
50e5b0a8f4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 13:12:44 -07:00
bbracker
efe9f5d857
make regression expect what buildroot is actually able to reach
2021-10-10 13:12:36 -07:00
David Harris
bfe8bf3855
Removed negedge flops from divider
2021-10-10 10:41:13 -07:00
bbracker
64a3043a88
update wave-do
2021-10-07 19:16:52 -04:00
James E. Stine
739e17ddac
Add generic wave command file
2021-10-06 13:17:49 -05:00
James E. Stine
658dcc8c1b
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
Ross Thompson
e4e353c186
updated fpga wavefile.
2021-10-03 12:14:22 -05:00
Ross Thompson
4c81d3453e
Added fpga wave file.
2021-10-03 11:56:11 -05:00
David Harris
9809e57d0c
Replacing XE and DE with SrcAE and SrcBE in divider
2021-10-03 11:11:53 -04:00
David Harris
8f36297569
Added suffixes to more divider signals
2021-10-03 00:32:58 -04:00
David Harris
24bb3f4baf
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
fe69513bb7
Partial divider cleanup
2021-10-02 20:55:37 -04:00
David Harris
d4437b842a
Divider code cleanup
2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d
Moved negating divider otuput to M stage
2021-10-02 10:03:02 -04:00
Ross Thompson
ec4a07de64
Movied tristate to test bench level.
2021-09-30 11:27:42 -05:00
Ross Thompson
db18aac9af
Partially sd card read on fpga.
2021-09-30 11:23:09 -05:00
David Harris
e1ad732178
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
Ross Thompson
99070127d8
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
Ross Thompson
5bdd6a9d0c
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
3a15cc7872
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
dd9fe60b28
Write of the SDC address register is correct. The command register is not yet working.
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The root problem is the command register needs to be reset at the end of the SDC transaction.
2021-09-24 18:48:11 -05:00
Ross Thompson
5663522a3f
Now have software interacting with the initialization and settting the address register.
2021-09-24 18:30:26 -05:00
Ross Thompson
232d4a554f
Have program which checks for sdc init and issues read, but read done is
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not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
af28cfb70c
Added SDC defines to each config mode.
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Added sd_top which is the sd card reader.
2021-09-24 12:24:30 -05:00
Ross Thompson
78028947bf
Updated Imperas test bench to work with the SDC reader.
2021-09-24 11:22:54 -05:00
Ross Thompson
d09b381183
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
b92070a67a
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
eb7b5f1d63
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
bbracker
92ddc9b20a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-15 17:31:11 -04:00
bbracker
b1be8f4858
fix regression
2021-09-15 17:30:59 -04:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
654f3d1940
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
David Harris
1847198da9
Cleaned up wally-arch test scripts
2021-09-13 00:02:32 -04:00
David Harris
cb624fe679
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
a31828e925
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6606eea27e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
