Ross Thompson
4af7a27d87
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Ross Thompson
0817ef20f1
Linux now boots fpga.
2021-10-26 16:49:16 -05:00
Ross Thompson
2f4ee26b60
Fixed issue with dtim (fpga) external abhlite select not triggering.
...
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
Ross Thompson
f7583d0e0d
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
Ross Thompson
6bad4058eb
Merge branch 'main' into fpga
2021-10-22 16:09:16 -05:00
kipmacsaigoren
611c4733cf
lowered number of paths to speed synth up and removed extra unnecessary report copying.
2021-10-22 15:25:11 -05:00
kipmacsaigoren
c2f4b49b15
removed reduntant definitions for FPU in MISA.
2021-10-22 15:18:25 -05:00
James E. Stine
a60e19dc3f
Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking
2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c
put the FMA priority encoders into their own module
2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98
Get rid of lint warning - still need more testing though
2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b
Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d
Fix fpdivsqrt lint error on CPA for convergence
2021-10-20 17:46:13 -05:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
f4e64c2eaf
Added debug signals to dcache.
2021-10-20 15:52:05 -05:00
David Harris
687703f0d8
removed .* from wallypipeliendsoc
2021-10-20 13:49:18 -07:00
davidharrishmc
923d03f657
Update README.md
2021-10-20 10:49:41 -07:00
kipmacsaigoren
742480d27d
Fixed path to src and config files, added mdu timing reports
2021-10-20 12:41:14 -05:00
kipmacsaigoren
b2deedd4b4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-20 12:15:53 -05:00
kipmacsaigoren
f0cf8bf17e
Removed historical outputs from repo
2021-10-20 12:15:40 -05:00
James E. Stine
7536e0a2ee
Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
2021-10-20 12:00:41 -05:00
David Harris
4aeadaacf0
moved coemark and testsBP to tests
2021-10-20 09:10:06 -07:00
David Harris
55fbafec74
moved imperas-riscv-tests to tests
2021-10-20 09:07:46 -07:00
David Harris
0e4f6392d6
Move tests into subdirectory and moved wavedrom out of project
2021-10-20 09:03:21 -07:00
David Harris
15e3b36a75
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-19 14:08:24 -07:00
David Harris
8747791bb8
radix 2 SRT checkin
2021-10-19 14:08:16 -07:00
bbracker
ca61d9b6b8
gitignore the addins folder because it contains external repos
2021-10-19 13:32:26 -07:00
James E. Stine
ed179b0bd9
Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
2021-10-19 12:09:43 -05:00
James E. Stine
b65a4bd040
Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
2021-10-19 11:58:06 -05:00
Ross Thompson
77a89c30de
Fixed bug with the external memory region selection.
...
Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
David Harris
8d08ca6a1e
Changed some flops to settable
2021-10-18 17:05:29 -07:00
David Harris
965946cae3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-18 16:54:08 -07:00
David Harris
df0b65e483
replaced flopenl with flopenr when clearing to 0
2021-10-18 16:53:18 -07:00
davidharrishmc
83af0740b5
Update README.md
2021-10-18 16:23:22 -07:00
David Harris
d0b9ebd2ef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-18 15:44:31 -07:00
David Harris
47f7a5db9c
Fixed multiplier and pointed arch tests to new path in addins
2021-10-18 15:43:59 -07:00
Ross Thompson
83a76ffb0c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-18 17:25:48 -05:00
Ross Thompson
d8d414665c
fixed issues with dc shell not liking modules with parameters without default values.
2021-10-18 17:24:15 -05:00
davidharrishmc
b8a126f311
Update README.md
2021-10-18 13:43:10 -07:00
davidharrishmc
091d8550d0
Update README.md
2021-10-18 13:39:40 -07:00
davidharrishmc
d1d4f9dc5f
Update README.md
2021-10-18 11:17:24 -07:00
davidharrishmc
5ceb7f1308
Update README.md
2021-10-18 09:52:40 -07:00
James E. Stine
d895fd7ee5
Sanitization some more on mult_cs.sv
2021-10-18 05:24:16 -05:00
James E. Stine
aafa988ca2
Update some on mult_cs and delete DW02_mult.v
2021-10-18 05:06:49 -05:00
James E. Stine
5a1835622c
Add hacky hand-made carry/save multiplier - will improve
2021-10-16 10:37:29 -05:00
Katherine Parry
33e5a078bf
cvtfp module documented
2021-10-14 15:25:31 -07:00
James E. Stine
6b30adb309
Clean up some signals - beautification onging
2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
ffcf5f5825
Fixed typo in imperas64mmu tests causing PMP tests not to run.
2021-10-14 13:42:24 -07:00
Skylar Litz
395e070917
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-13 15:38:32 -07:00
Skylar Litz
d639222519
add StallM signal back to DivStartE control
2021-10-13 15:34:40 -07:00
