Ross Thompson 2f4ee26b60 Fixed issue with dtim (fpga) external abhlite select not triggering. ... Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.		2021-10-25 14:51:54 -05:00
..
old	Divider FSM simplification	2021-10-10 22:24:14 -07:00
slack-notifier	added slack notifier for long sims	2021-06-22 08:31:41 -04:00
wave-dos	Removed negedge flops from divider	2021-10-10 10:41:13 -07:00
fpga-wave.do	Fixed issue with dtim (fpga) external abhlite select not triggering.	2021-10-25 14:51:54 -05:00
linux-wave.do	update wave-do	2021-10-07 19:16:52 -04:00
regression-wally.py	change infrastructure to expect only 6.3 million from buildroot	2021-10-12 10:41:15 -07:00
sim-buildroot	start to add buildroot testbench	2021-04-16 23:27:29 -04:00
sim-buildroot-batch	start to add buildroot testbench	2021-04-16 23:27:29 -04:00
sim-fp64	Update to fpdivsqrt to go on posedge as it should. Also an update to	2021-10-13 17:14:42 -05:00
sim-fp64-batch	Update to fpdivsqrt to go on posedge as it should. Also an update to	2021-10-13 17:14:42 -05:00
sim-wally	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
sim-wally-batch	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
wally-buildroot-batch.do	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
wally-buildroot.do	restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair	2021-09-04 19:45:04 -04:00
wally-fp64-batch.do	Update to fpdivsqrt to go on posedge as it should. Also an update to	2021-10-13 17:14:42 -05:00
wally-fp64.do	Update to fpdivsqrt to go on posedge as it should. Also an update to	2021-10-13 17:14:42 -05:00
wally-pipelined-batch.do	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
wally-pipelined-fpga.do	Fixed issue with dtim (fpga) external abhlite select not triggering.	2021-10-25 14:51:54 -05:00
wally-pipelined.do	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
wave-all.do	Fixed busybear by restoring InstrValidW needed by testbench	2021-07-13 14:17:36 -04:00
wave.do	Merge branch 'main' into fpga	2021-10-11 18:17:58 -05:00