Ross Thompson
04eb302925
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Thomas Fleming
5bff582608
Write PCM to TVAL registers
2021-04-22 16:17:57 -04:00
Thomas Fleming
07770a46d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 15:37:19 -04:00
Thomas Fleming
74fb1dccad
Prepare to squash bad ahb accesses
2021-04-22 15:36:45 -04:00
Thomas Fleming
c055ab272d
Clean up lint errors in fpu and muldiv
...
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
2021-04-22 15:36:03 -04:00
Domenico Ottolia
787ae978d7
Fix misa synthesis bug (for real now)
2021-04-22 15:35:20 -04:00
Thomas Fleming
e7822ce20c
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
848508530c
Pass lint-wally arguments to verilator
2021-04-22 13:39:20 -04:00
Jarred Allen
8baa2a350d
Add buildroot to regression test
2021-04-22 13:34:56 -04:00
Thomas Fleming
805ac5dbd7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-22 13:20:12 -04:00
Thomas Fleming
f9e071baf8
Temporarily disable rv64 mmu test
...
Will restore once cache revamp is pushed
2021-04-22 13:19:18 -04:00
Noah Boorstin
3bf79923d4
small parser fix
2021-04-22 12:06:54 -04:00
bbracker
c796547156
greatly improved PLIC register interface
2021-04-22 11:22:01 -04:00
Ross Thompson
7c8d2e9b78
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Thomas Fleming
d22f0f9d63
Refactor tlb_ram to use flop primitives
2021-04-22 01:52:43 -04:00
Thomas Fleming
4d4ca24640
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Domenico Ottolia
939e36a151
Fix misa bug
2021-04-22 00:59:07 -04:00
Thomas Fleming
88bd151d55
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ifu/ifu.sv
2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Ross Thompson
50e893eec9
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Teo Ene
6da8530104
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-21 16:06:33 -05:00
Teo Ene
008b308b79
Fixed most relevant remaining synthesis compilation warnings with Ben
2021-04-21 16:06:27 -05:00
Noah Boorstin
0afd5ae5f6
buildroot: add workaround for weird initial MSTATUS state
2021-04-21 16:03:42 -04:00
Ross Thompson
269ea7997c
major progress.
...
It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Domenico Ottolia
82320033d5
Add tests for stval and mtval
2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19
Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac
Add tests for sepc register
2021-04-20 23:50:53 -04:00
Ross Thompson
a861a37b72
Why was the linter messed up?
...
There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Domenico Ottolia
e02ff60b07
Fix synthesis warnings for privileged unit (replace 'initial' settings)
2021-04-20 17:57:56 -04:00
Noah Boorstin
cd6cb1f66c
really small parser update
2021-04-19 23:17:37 -04:00
Noah Boorstin
c7a09d2359
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Jarred Allen
59b340dac9
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Katherine Parry
204e5cb018
fixed synth bugs in fpu
2021-04-19 00:39:16 +00:00
Noah Boorstin
10c7ac7f73
slowly more buildroot progress
2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c
neat verilog thing
2021-04-18 17:48:51 -04:00
Noah Boorstin
0e71c212b2
buildroot parser: more updates
...
5 -> 23 instructions!
2021-04-17 17:44:46 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
Noah Boorstin
0931f0d977
busybear testgen updates
...
and start working on qemu parser
2021-04-16 15:34:55 -04:00
Jarred Allen
3868a82932
dcache lints
2021-04-15 21:13:56 -04:00
Jarred Allen
32cfbc6926
Enable linting of blocks not yet in the hierarchy
2021-04-15 21:13:40 -04:00
bbracker
11cf251378
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00
Add tests for scause and ucause
2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Domenico Ottolia
70b79ca301
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 16:57:27 -04:00
Domenico Ottolia
8c4cfa5f69
Add 32 bit privileged tests
2021-04-15 16:55:39 -04:00
Teo Ene
a9c6d357d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 15:29:09 -05:00
