Configurable RISC-V Processor
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Ross Thompson a861a37b72 Why was the linter messed up?
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Why was the linter messed up? 2021-04-20 22:06:12 -05:00
.gitignore buildroot parser: more updates 2021-04-17 17:44:46 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

riscv-wally

Configurable RISC-V Processor