Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
605 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
0e71c212b2
Go to file
Noah Boorstin 0e71c212b2 buildroot parser: more updates 
5 -> 23 instructions!
2021-04-17 17:44:46 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined buildroot: sim is now running! 2021-04-17 14:44:32 -04:00
.gitignore buildroot parser: more updates 2021-04-17 17:44:46 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor