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Configurable RISC-V Processor
635 Commits 4 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
269ea7997c
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Ross Thompson 269ea7997c major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined major progress. 2021-04-21 08:39:54 -05:00
.gitignore buildroot parser: more updates 2021-04-17 17:44:46 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor