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Configurable RISC-V Processor
612 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Domenico Ottolia d5f86fadac Add tests for sepc register
2021-04-20 23:50:53 -04:00
sky130
wally-pipelined Add tests for sepc register 2021-04-20 23:50:53 -04:00
.gitignore buildroot parser: more updates 2021-04-17 17:44:46 -04:00
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riscv-wally

Configurable RISC-V Processor