bbracker
a45b61ede9
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
bbracker
142b02b30a
improved PLIC test organization
2021-05-21 15:13:02 -04:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
114bba8370
small bit of busybear debug progress
2021-05-19 20:18:00 -04:00
James E. Stine
058b265d18
Update rv64icfd batch script
2021-05-18 16:01:53 -05:00
David Harris
5f214d60b6
Removed rv64wally
2021-05-18 14:08:46 -04:00
David Harris
433ea61d9e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
2021-05-18 14:01:19 -04:00
bbracker
86d55cd07a
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
2021-05-17 19:25:54 -04:00
bbracker
69ef758e78
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
2021-05-17 18:44:47 -04:00
David Harris
1aa1908994
Deleted vish_stacktrace
2021-05-17 18:39:01 -04:00
Elizabeth Hedenberg
853c9243c1
commit ehedenberg coremark
2021-05-17 18:02:35 -04:00
James E. Stine
8822bdd6ad
Cleanup of regression
2021-05-17 16:58:15 -05:00
James E. Stine
97cbdae674
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
a191978a97
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-14 07:40:08 -04:00
Thomas Fleming
1fc607b399
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Jarred Allen
dc41623754
Minor fixes in regression
2021-05-09 13:57:09 -04:00
Jarred Allen
788680fa4d
Fix bug in regression script
2021-05-06 12:56:57 -04:00
Jarred Allen
15da77fe15
Clean up regression script and document it
2021-05-04 18:58:59 -04:00
Thomas Fleming
d53afc8510
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Elizabeth Hedenberg
08bfaeffe3
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
81ed9b5d06
coremark directory changes
2021-05-03 19:35:06 -04:00
Ross Thompson
21c0ee0cf2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Jarred Allen
a21b84e2ad
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
1db608fbc6
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
fdf4954a20
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Noah Boorstin
c9fcd3405d
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
Domenico Ottolia
99a927be47
Add medeleg tests
2021-04-29 15:02:36 -04:00
Jarred Allen
c6996ce39d
Remove signal which no longer exists from default waves, so sim-wally works
2021-04-29 14:41:10 -04:00
Thomas Fleming
d29ddddc3f
Remove unused waves from .do files
2021-04-29 02:19:46 -04:00
Thomas Fleming
6515c0b9ed
Add mmu waves (commented) to busybear
2021-04-28 20:01:05 -04:00
Ross Thompson
d191bc6cc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Noah Boorstin
24bbb674d3
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Noah Boorstin
9cbc769083
minor busybear fixes
2021-04-26 13:24:39 -04:00
Ross Thompson
44d28dbd1c
Icache integrated!
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Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
46a1616079
thomas fixed it before I did
2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96
do script refactor
2021-04-24 09:32:09 -04:00
Ross Thompson
d7fea1ba3c
almost working icache.
2021-04-23 16:47:23 -05:00
Jarred Allen
9a88d83851
Remind people to run make allclean when a regression fails
2021-04-22 19:21:00 -04:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
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Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
