bbracker
3de8461f3c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 05:40:49 -04:00
bbracker
c9775de3b2
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
2021-07-20 05:40:39 -04:00
James E. Stine
b36d6fe1be
slight mod to fpdiv - still bug in batch vs. non-batch
2021-07-20 01:47:46 -04:00
bbracker
5347a58192
major fixes to CSR checking
2021-07-20 00:22:07 -04:00
Ross Thompson
ae2371f2ce
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
Ross Thompson
07c47f0034
Restored TIM range.
2021-07-19 21:17:31 -05:00
bbracker
a01fea69dd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 19:30:40 -04:00
bbracker
af5d319f08
change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)
2021-07-19 19:30:29 -04:00
David Harris
678f705415
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 18:19:59 -04:00
David Harris
b2f7952b3d
Added cache configuration to config files
2021-07-19 18:19:46 -04:00
bbracker
aeaf4a31f0
MemRWM shouldn't factor into PCD checking
2021-07-19 18:03:30 -04:00
bbracker
30c381c707
create qemu_output.txt
2021-07-19 18:02:41 -04:00
bbracker
45b78dd8b3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 17:11:49 -04:00
bbracker
5911029d2b
make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
2021-07-19 17:11:42 -04:00
Kip Macsai-Goren
3a73ae0a8b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 16:46:46 -04:00
bbracker
bb2e3b1e02
remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux
2021-07-19 16:22:05 -04:00
bbracker
78e513160e
put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
2021-07-19 16:19:24 -04:00
bbracker
009e9d97bf
adapt testbench to removal of ReadDataWEn signal
2021-07-19 15:42:14 -04:00
bbracker
02de6014b2
adapt testbench to removal of signal
2021-07-19 15:41:50 -04:00
bbracker
76be84fa92
whoops MTIMECMP is always 64 bits
2021-07-19 15:40:53 -04:00
bbracker
fb6e618b1c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:13:14 -04:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
c1c564d54c
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
5edd513f8c
Furture simplification of the dcache ReadDataW update.
2021-07-19 12:46:31 -05:00
Ross Thompson
5754b5f25f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-19 12:32:35 -05:00
Ross Thompson
2ee97efb9c
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
bbracker
8cbd83e804
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 13:21:04 -04:00
bbracker
2702064dda
change buildroot expectations to match reality
2021-07-19 13:20:53 -04:00
Ross Thompson
6ccbdc372d
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
986b7a8252
change sram1rw to have a small delay so that we don't have signals changing on clock edges
2021-07-19 11:30:07 -04:00
David Harris
1b55f584c7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 10:34:18 -04:00
James Stine
62b4ef6953
delete sbtm_a4 and sbtm_a5 as they are not needed
2021-07-19 08:06:00 -05:00
James Stine
892bc68918
remove sbtm3.sv - not needed
2021-07-19 08:00:53 -05:00
James Stine
55f2720f89
update part I on sbtm change
2021-07-19 07:59:27 -05:00
David Harris
0c41b8102d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 00:25:06 -04:00
Katherine Parry
8d101548f1
FDIV and FSQRT passes when simulating in modelsim
2021-07-18 23:00:04 -04:00
bbracker
64a81941ff
change memread testvectors to not left-shift bytes and half-words
2021-07-18 21:49:53 -04:00
David Harris
4729a72167
Updated FMA1 with parameterized size
2021-07-18 20:40:49 -04:00
bbracker
f4f3ef0307
linux testbench progress
2021-07-18 18:47:40 -04:00
David Harris
398e9583e9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-18 17:36:29 -04:00
David Harris
f22b6e7397
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
Katherine Parry
3527620c0b
fdivsqrt inegrated, but not completley working
2021-07-18 14:03:37 -04:00
David Harris
e31d2ef9f5
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
e962324d00
LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall
2021-07-18 03:51:30 -04:00
David Harris
40c5d3ced7
HPTW: Simpliifieid PRegEn
2021-07-18 03:35:38 -04:00
David Harris
a5a7be3e03
Removed EndWalk signal and simplified TLBMissReg
2021-07-18 03:26:43 -04:00
Ross Thompson
a0017e39e2
Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
2021-07-17 21:02:24 -05:00
Ross Thompson
d0ed6e250a
Fixed LRSC in 64bit version. 32bit version is broken.
2021-07-17 20:58:49 -05:00
David Harris
3be88117c5
added lrsc.sv
2021-07-17 21:15:08 -04:00
David Harris
c29a2ff8df
Started atomics
2021-07-17 21:11:41 -04:00
David Harris
3783b5dc00
moved subwordread to lsu
2021-07-17 20:37:20 -04:00
David Harris
84f579038c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-17 20:01:23 -04:00
David Harris
d441d4270c
LSU cleanup
2021-07-17 20:01:03 -04:00
David Harris
f21582906f
Pushing HPTWPAdrM flop into LSUArb
2021-07-17 19:39:18 -04:00
David Harris
989bb7c01b
Simplified VPN case statement
2021-07-17 19:34:01 -04:00
Ross Thompson
379cf6c188
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-17 18:27:44 -05:00
David Harris
25450bd7c1
Finished HPTW TranslationPAdr simlification
2021-07-17 19:27:24 -04:00
Ross Thompson
053e9593af
Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before.
2021-07-17 18:26:29 -05:00
David Harris
217bf37668
Further TranslationVAdr simplification
2021-07-17 19:24:37 -04:00
David Harris
d8397b5e8b
Continued Translation Address Cleanup of TranslationPAdrMux
2021-07-17 19:16:56 -04:00
David Harris
6f73844427
Continued Translation Address Cleanup
2021-07-17 19:09:13 -04:00
David Harris
2e2e948023
Refining address interface between HPTW and LSU
2021-07-17 19:02:18 -04:00
David Harris
12cfe91362
Fixed bad register in I-FSD-01 Imperas test.
2021-07-17 17:08:07 -04:00
David Harris
e3bf8db80b
trap.sv comment cleanup
2021-07-17 16:01:07 -04:00
David Harris
b2c2194478
trap.sv cleanup
2021-07-17 15:57:10 -04:00
David Harris
777e983c19
Finished removing PageTableEntry redundant signals from hptw
2021-07-17 15:50:52 -04:00
David Harris
348e69c096
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:24:26 -04:00
David Harris
49ec45d04d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
David Harris
162afcc994
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-17 15:11:43 -04:00
David Harris
e55546da34
hptw: Propagating PageTableEntryF removal through IFU
2021-07-17 15:04:39 -04:00
David Harris
bf56000f4e
hptw: Propagating PageTableEntryF removal through LSU
2021-07-17 15:01:01 -04:00
bbracker
56f246463f
separated buildroot debugging from buildroot logging
2021-07-17 14:52:34 -04:00
David Harris
d6b8a5e595
hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE
2021-07-17 14:48:44 -04:00
bbracker
6feb95c779
swapped out linux testbench signal names
2021-07-17 14:48:12 -04:00
bbracker
d85da77069
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-17 14:46:38 -04:00
bbracker
ac908bc2e4
swapped out linux testbench signal names
2021-07-17 14:46:18 -04:00
David Harris
ef03ec275c
hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states
2021-07-17 14:36:27 -04:00
David Harris
d19679f213
hptw: Eliminated A and D bit faults while walking page table, per spec
2021-07-17 14:29:20 -04:00
David Harris
ad44835e6e
hptw: Simplified TranslationVAdr calculation based just on DTLBWalk
2021-07-17 14:16:33 -04:00
David Harris
af02437c3a
hptw: renamed DTLBMissQ to DTLBWalk
2021-07-17 14:13:00 -04:00
David Harris
8e966b37f2
hptw: renamed ADRE to ADR
2021-07-17 14:02:59 -04:00
David Harris
95d49e4e9b
hptw: replaced PreviousWalkerState with a PageType FSM
2021-07-17 13:54:58 -04:00
David Harris
964f0d9f53
hptw: removed ITLBMissFQ
2021-07-17 13:44:08 -04:00
David Harris
9741b01465
hptw: minor cleanup
2021-07-17 13:40:12 -04:00
David Harris
ee784c19a5
hptw: Simplifed out AnyTLBMiss
2021-07-17 12:07:51 -04:00
David Harris
40989c4e3d
hptw: Renamed Memstore to MemWrite
2021-07-17 12:01:43 -04:00
David Harris
ddd9110f7b
hptw: Merged RV32/64 FSMs
2021-07-17 11:55:24 -04:00
David Harris
36a8d23222
hptw: FSM simplification
2021-07-17 11:41:43 -04:00
David Harris
6d28f3fe08
hptw: default state should be unreachable
2021-07-17 11:33:16 -04:00
David Harris
ef83a44c4d
hptw: factored Misaligned
2021-07-17 11:31:16 -04:00
David Harris
e3b26b7b23
hptw: factored HPTWRead
2021-07-17 11:25:59 -04:00
David Harris
1bbc932bfd
hptw: factored HPTWRead
2021-07-17 11:25:52 -04:00
David Harris
37cc2ca30f
hptw: factored pregen
2021-07-17 11:11:10 -04:00
David Harris
1595e4f992
HPTW: more cleanup
2021-07-17 04:55:01 -04:00
David Harris
b74f3b14ec
HPTW: factored out DTLBWrite/ITLBWrite
2021-07-17 04:44:23 -04:00
David Harris
9775294a6f
HPTW: factored out PageTableENtry
2021-07-17 04:40:01 -04:00
David Harris
f168bd6749
more cleaning up FSM
2021-07-17 04:35:51 -04:00
David Harris
e2600bc55d
cleaning up FSM
2021-07-17 04:26:41 -04:00
David Harris
52a7dd9ac0
Simplify FSM
2021-07-17 04:12:31 -04:00
David Harris
31a3b39e5c
Pulled TranslationPAdr mux out of HPTW FSM
2021-07-17 04:06:26 -04:00
