Rose Thompson
337903d8dd
More cache simplifications.
2023-11-27 14:59:42 -06:00
Rose Thompson
08549446ef
Reduced cache fsm complexity.
2023-11-27 13:13:36 -06:00
Rose Thompson
c3da4c3c31
Clarified names in cacheway.
2023-11-27 12:56:11 -06:00
Rose Thompson
d7ef490c12
Sutble bug in the cacheway logic for cacheline invalidation.
2023-11-27 01:27:09 -06:00
Rose Thompson
58d89cc347
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-11-21 10:48:05 -06:00
David Harris
f89fd8a7fe
removed unused cache signals
2023-11-20 23:16:35 -08:00
Rose Thompson
1acc3951c8
More simplifications.
2023-11-21 00:19:24 -06:00
Rose Thompson
1d811b085c
More cleanup.
2023-11-21 00:14:59 -06:00
Rose Thompson
d2a747bf3d
cleanup.
2023-11-20 23:59:40 -06:00
Rose Thompson
70eb110a9c
More optimizations to simplify cmo logic.
2023-11-20 22:13:31 -06:00
Rose Thompson
52ac07ce8d
Removed the CMO_WRITEBACK state from the cache and unused signals.
2023-11-20 20:56:30 -06:00
Rose Thompson
667fe035c0
Simplified CMO.Zero fsm implementation slightly.
2023-11-20 17:01:43 -06:00
Rose Thompson
23e05cb8b2
Finally have the cbo way muxing controls reduced to something sane.
2023-11-20 11:28:03 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
David Harris
1f2899de14
Modified rams to take USE_SRAM rather than P to facilitate synthesis
2023-11-03 05:44:13 -07:00
Rose Thompson
dce3c85105
Progress.
2023-10-27 16:31:22 -05:00
David Harris
6e7c0547a1
Modified log2 coding to avoid synthesis warning
2023-10-19 11:16:02 -07:00
Ross Thompson
11a3fd9314
Slight modification to cachefsm.
2023-09-05 14:07:58 -05:00
Ross Thompson
85ba53eeaf
Merge pull request #406 from magpyed/cachesim_fix
...
Properly gate LRUWriteEn with ~FlushStage
2023-09-05 11:10:58 -05:00
Limnanthes Serafini
6c78942685
Properly gate LRUWriteEn with ~FlushStage
2023-09-01 23:31:02 -07:00
David Harris
e75ceb044f
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
Ross Thompson
99455ad851
Fixed minor performance bug with CBOZ.
2023-08-24 17:08:20 -05:00
Ross Thompson
914b6f9734
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
Ross Thompson
c2a9fbb1fc
Fixed bug with the cbo.inval clearing already cleared lines.
2023-08-21 17:51:51 -05:00
Ross Thompson
05d590b0b9
Fixed issue when with flush miss.
2023-08-18 16:36:13 -05:00
Ross Thompson
fc3fccafe9
Now we have invalidate, clean, and flush working.
2023-08-18 16:32:22 -05:00
Ross Thompson
5c408454b8
Might have working cbo clean and flush instructions.
2023-08-18 14:48:21 -05:00
Ross Thompson
21129dde71
Fixed cbo instruction decode.
2023-08-18 11:32:30 -05:00
Ross Thompson
072126b967
Found first bug in CMO implementation.
2023-08-17 16:57:54 -05:00
Ross Thompson
f9df1fda23
CMOZ now implemented in the D cache.
2023-08-17 12:46:40 -05:00
Ross Thompson
624b3e3ab2
Added clean and flush to cache fsm.
2023-08-16 14:23:56 -05:00
Ross Thompson
5281077531
More progress towards cmo.
2023-08-15 18:17:15 -05:00
Ross Thompson
9f37fef145
The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
2023-08-14 16:39:18 -05:00
Ross Thompson
0eac74ac7b
Initial CMO implementation. Just adds control signals into the L1 caches.
2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7
Cache cleanup.
2023-07-31 14:12:53 -05:00
Ross Thompson
d04d2afed2
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Ross Thompson
50bc679fef
Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.
2023-07-14 16:31:44 -05:00
Ross Thompson
38f32805ae
Created separate temporary testbench for xcelium.
2023-07-11 15:07:33 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
75b5c23edd
Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
2023-06-15 14:05:44 -05:00
Ross Thompson
009d8966e9
Got the srams parameterized correctly now.
2023-06-15 13:42:24 -05:00
Ross Thompson
b8a243827b
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Harshini Srinath
570a628198
Update subcachelineread.sv
...
Code clean up
2023-06-09 08:50:51 -07:00
Harshini Srinath
c49232f0d2
Update cacheway.sv
...
Code clean up
2023-06-09 08:48:11 -07:00
Harshini Srinath
e7fb7403ef
Update cacheLRU.sv
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Code clean up
2023-06-09 08:43:38 -07:00
Harshini Srinath
19c1a0f99b
Update cache.sv
...
Formatting clean up
2023-06-09 08:39:57 -07:00
Ross Thompson
052bc95966
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Ross Thompson
7c0eb16e62
Fixed bug in cacheLRU when NUMWAYS = 2.
2023-04-27 14:30:01 -05:00
Alec Vercruysse
5612f30029
Cacheway Exclude FlushStage=1 when SetValidWay=1
...
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).
My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
2023-04-25 20:30:46 -07:00
Alec Vercruysse
857956ac1e
Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign
...
FlushWay is always 1 for one way, but by default it is only 1 for
way 0.
The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
2023-04-25 17:02:53 -07:00
