Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 13:34:28 +00:00
Code Issues Packages Projects Releases Wiki Activity
6,984 Commits 4 Branches 2 Tags 52 MiB
310b700550
Commit Graph

228 Commits

Author SHA1 Message Date
Ross Thompson
310b700550 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d Working CBO tests for 64 bit! 2023-08-21 12:55:07 -05:00
Ross Thompson
5ed096e4bc Made a bunch of progress towards getting cbo instructions tested. 2023-08-21 11:46:21 -05:00
David Harris
c137a1c8cf Fixed timer interrupt testing 2023-06-09 17:20:41 -07:00
David Harris
f68b9c224a Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
David Harris
b70b0c7c5e Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
David Harris
19096a812a Added Zifencei ISA to tests where necessary to support new compiler 2023-05-16 11:18:27 -07:00
David Harris
0a7a159d69 Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile 2023-05-14 06:58:29 -07:00
Kip Macsai-Goren
34200e8c76 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02 renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
b2d6084eea removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
a82c0a7780 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
e0b938b409 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
a899606c2b Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
19305fe60a Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
Kip Macsai-Goren
a7c9d3d37b ported medelg fixes to 32 bit tests. Requires a make allclean 2023-03-29 16:31:28 -07:00
Kip Macsai-Goren
2e151b6b08 updated tests to reflect non-writeable bits of deleg 2023-03-29 15:24:00 -07:00
David Harris
2e5c50e24a Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
e8904411ce Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
Kip Macsai-Goren
106ed02a7e Revert "added premilinary boundary ccrossing cases" 
This reverts commit 7870148814.
 2023-03-24 11:27:41 -07:00
Kip Macsai-Goren
758da62a9f ported fixes to 32 bit tests 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
ff59fefcc9 replaced inerrupt tests with allowed versions 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
6f15ae1225 Added cause_s_soft_from_m_interrupt 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
7870148814 added premilinary boundary ccrossing cases 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
db6caedfec added in the CSR name for stimecmp(h) 2023-03-04 15:53:03 -08:00
Kip Macsai-Goren
ab6b953a4b removed changes to counteren from stimecmp tests 2023-03-04 15:46:57 -08:00
Kip Macsai-Goren
ac5c53a870 Added correct causing and handling of S time interrupts to test suite. 2023-03-04 15:04:17 -08:00
David Harris
f0c0111ab0 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00
David Harris
4883351bd2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 18:18:53 -08:00
Kip Macsai-Goren
ee1bcf62ee Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. 2023-01-28 17:29:35 -08:00
David Harris
cea89f27cf Removed unused WALLY test references 2023-01-27 07:25:04 -08:00
David Harris
2af94bf283 Removed unused reference files 2023-01-27 07:21:55 -08:00
Kip Macsai-Goren
964084f0b3 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
a37bde7452 updated trap handler alignemnts to 64 bytes in priv tests 2022-12-22 14:23:04 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
4c81b6fa5f added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
4ab99904a4 added all 32 bit tests to 64 bit periph tests except gpio 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
51e78d9e48 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
540d6c2f41 added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
9b1765ce92 added tests for invalid address being written to satp. Not passing regression 2022-11-27 13:22:35 -08:00
Kip Macsai-Goren
21e045eb7d added potential fix to overrun error and fifo interrupt error. test passes 2022-11-06 22:01:02 -08:00
Kip Macsai-Goren
90ef371abc fixed fifo timout handling. error now in data ready interrupt 2022-11-05 13:34:24 -07:00
Kip Macsai-Goren
c06da6e6fe fixed broken instructions so make works. 2022-11-03 23:06:20 +00:00
Ross Thompson
103514a8e0 More outline for uart timeout interrupt. 2022-10-28 13:53:56 -05:00
Ross Thompson
21eca47d2e Untested change to uart test for outline of how to handle rx fifo timeout. 2022-10-28 13:31:16 -05:00
Kip Macsai-Goren
6e45698b86 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00