Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
11a057b0b3
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
f1cc7dd5a3
Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
Rose Thompson
1eff86b7ae
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
c463201d68
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
bb74a0f96b
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Jacob Pease
a506d76149
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
...
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Ross Thompson
24916d42e2
Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw.
2024-06-19 11:40:02 -07:00
Ross Thompson
ab1af0fabf
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2024-06-19 09:25:39 -07:00
David Harris
3fa37b0233
Lint cleanup
2024-06-18 06:15:17 -07:00
David Harris
cac67aae4f
Lint cleanup
2024-06-18 05:58:54 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Rose Thompson
04744032d8
Updated more signal names to match book.
2024-06-02 16:59:11 -05:00
Rose Thompson
b45b7ff7d6
Signal name changes to match book.
2024-06-02 16:32:25 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b
Have rvvi to ethernet working.
...
Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
2024-05-24 15:52:13 -05:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
...
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
Rose Thompson
e5b8fd35b0
Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.
2024-05-22 09:56:12 -05:00
Rose Thompson
b116c0c902
Lots of progress on the rvvisynth to ethernet packetizer.
...
Almost producing axi4 commands.
2024-05-21 18:23:42 -05:00
Rose Thompson
d1141237ee
Removed prefix from rvvi hierarchy so it works without testbench.
2024-05-21 16:20:53 -05:00
Rose Thompson
8fd278b322
Fixed some references to rvvi.
2024-05-21 16:15:05 -05:00
Rose Thompson
ea5d780adf
Closer to synthesized rvvi
2024-05-21 12:42:43 -05:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
David Harris
c0afb44ed4
Tied dangling signals to 0 for some configs to make VCS lint happy
2024-04-28 22:50:36 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
slmnemo
39ae26a897
Added documentation for known Verilator hierarchy bug
2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e
Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory
2024-04-12 21:58:20 -07:00
Rose Thompson
29db2cd931
Basic hardware tracer works!
...
Next step is to package the buses into packets to ethernet transmission.
2024-03-08 12:38:27 -06:00
Rose Thompson
140e64772e
Merge branch 'main' into rvvi
2024-03-08 10:16:31 -06:00
Rose Thompson
aa15a63d9c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-31 13:12:32 -06:00
David Harris
f37c7bb1f6
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
2024-01-30 06:27:18 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
fd032a7e10
Draft implementation of synth rvvi.
2024-01-24 15:06:13 -06:00
Rose Thompson
0babb011c2
Synthesizable rvvi tracer output G/FPRs.
2024-01-23 16:27:50 -06:00
Rose Thompson
cacbcb6fcf
Created the basic synthesizable wally tracer for fpga.
2024-01-23 16:16:29 -06:00
Rose Thompson
4c2ba2b0b4
Added StoreStall back to csrc.
2024-01-18 14:43:34 -06:00
Rose Thompson
edc56c669e
Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
2024-01-05 17:10:14 -06:00
David Harris
2c2f692f3a
Moved forwarding logic into controller
2023-12-26 21:17:01 -08:00
David Harris
8eace30f49
Moved UnalignedPCNextF mux into IFU
2023-12-20 16:18:31 -08:00
Rose Thompson
9f4c32d49c
Merge branch 'main' of github.com:ross144/cvw
2023-12-13 20:32:59 -06:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
Rose Thompson
13bb5d845b
On the way to solving the store delay hazard.
2023-12-13 10:39:01 -06:00
David Harris
d3ce683e06
Removed other unused signals from Verilog
2023-11-20 23:37:56 -08:00
David Harris
8ba0336c6f
Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e
2023-11-14 11:01:58 -08:00
naichewa
e3d8162279
harris code review 3
2023-11-01 10:14:15 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
