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1730 Commits

Author SHA1 Message Date
bbracker
9cdbd9a0bf remove unused scripts 2021-10-24 15:19:03 -07:00
bbracker
4100ed9a7a update debugger script to new style 2021-10-24 15:18:44 -07:00
bbracker
3c118437de fix typo 2021-10-24 15:05:00 -07:00
bbracker
eb9740bc31 manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
0a32d79370 checkpoint generator bugfix 2021-10-24 14:46:56 -07:00
Ross Thompson
87aaec3b6c Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
4544d28bc9 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
23bff55c6e increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
dcd4d9dd9f add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
35ccab0e29 revamp linux testvector generation for refactoring checkpoint generation 2021-10-24 06:14:11 -07:00
bbracker
366cb12a13 buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
f6911be937 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
3b63dde570 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
d6fb441666 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
67f3fc9962 wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
106982e493 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34 more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
bb4ad264ce IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
b6bb33ecef lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
5e961973cb IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
708b914a65 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
817795f619 Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
2abec36221 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
6ae9aa7d80 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2 FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
5235e61d9e Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
bf3eb7b814 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
ff409d4fe7 Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
kipmacsaigoren
c2f4b49b15 removed reduntant definitions for FPU in MISA. 2021-10-22 15:18:25 -05:00
James E. Stine
a60e19dc3f Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
David Harris
687703f0d8 removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
James E. Stine
7536e0a2ee Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. 2021-10-20 12:00:41 -05:00
David Harris
4aeadaacf0 moved coemark and testsBP to tests 2021-10-20 09:10:06 -07:00
David Harris
0e4f6392d6 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00
David Harris
8747791bb8 radix 2 SRT checkin 2021-10-19 14:08:16 -07:00
James E. Stine
ed179b0bd9 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
b65a4bd040 Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
David Harris
8d08ca6a1e Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
df0b65e483 replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
David Harris
d0b9ebd2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
47f7a5db9c Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
d8d414665c fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
James E. Stine
d895fd7ee5 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
aafa988ca2 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
5a1835622c Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
33e5a078bf cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
6b30adb309 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
ffcf5f5825 Fixed typo in imperas64mmu tests causing PMP tests not to run. 2021-10-14 13:42:24 -07:00
Skylar Litz
395e070917 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
d639222519 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
eb64a7f0c9 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
bbracker
886a650da4 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Shreya Sanghai
d783acbbc5 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Katherine Parry
09f51871c5 lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
4ea56ac68b some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
Shreya Sanghai
51185478df made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
295a3c7af2 actually added redundant mul 2021-10-11 11:29:13 -07:00
David Harris
f9b37c3ce1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 11:21:39 -07:00
David Harris
062fbfb610 Extended lint to check rv32/64g (including fpu. Not clean yet. 2021-10-11 11:20:42 -07:00
Shreya Sanghai
324230e2f9 added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
fc39f77cba Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
David Harris
8a64675b02 intdiv cleanup 2021-10-11 08:14:21 -07:00
David Harris
a8ce4568aa Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
a077735ecc Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
James E. Stine
11cf3d97c5 Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH 2021-10-10 15:44:01 -05:00
bbracker
50e5b0a8f4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00
bbracker
efe9f5d857 make regression expect what buildroot is actually able to reach 2021-10-10 13:12:36 -07:00
David Harris
266c706804 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
77f1ae54d8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
8eff03bf1a simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
93e6ec96a7 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6d2d93deeb Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
2d09994a91 Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
644af40855 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
e93014d6d8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
e8d013b106 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
179223bef0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 10:10:06 -07:00
bbracker
5a987cf0ca use correct string formatting function 2021-10-10 10:09:59 -07:00
David Harris
99fd79c20b Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
44b023ace1 FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
bbracker
54e0e8eb5b make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00
kipmacsaigoren
086e6d130a rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
kipmacsaigoren
8e35701103 Merging new changes into the old one's I've made in the OKstate servers 2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
381a8fcd27 updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully. 2021-10-08 15:40:18 -07:00
Kip Macsai-Goren
3623dfa51e removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00
kipmacsaigoren
3103b78493 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-08 12:01:44 -05:00
David Harris
7e340d16fd moved fp vectors into vectors subdirectory 2021-10-07 23:28:06 -04:00
David Harris
626780381a Included TestFloat and SoftFloat 2021-10-07 23:03:45 -04:00
bbracker
64a3043a88 update wave-do 2021-10-07 19:16:52 -04:00
bbracker
6e75f82589 update linux wave-do 2021-10-07 19:15:11 -04:00
bbracker
25e0745a6a fix div restarting bug 2021-10-07 18:55:00 -04:00
James E. Stine
0c408a9816 update scripts 2021-10-07 15:14:54 -05:00
bbracker
d45b8fa4dc more checkpoint reformatting 2021-10-07 04:27:45 -04:00
bbracker
a9052cb455 don't log rf[0] to checkpoint 2021-10-07 00:58:33 -04:00
bbracker
ec1e04e8b8 update linker scripts to look for vmlinux files 2021-10-06 16:55:38 -04:00
bbracker
1a1c4f28f4 update linker scripts to look for vmlinux files 2021-10-06 16:51:31 -04:00
James E. Stine
4dcfcfacfc TV for conversion and compare 2021-10-06 14:38:32 -05:00
James E. Stine
739e17ddac Add generic wave command file 2021-10-06 13:17:49 -05:00
James E. Stine
658dcc8c1b Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
kipmacsaigoren
086a0234ba Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-06 11:52:34 -05:00
James E. Stine
4ece7b5341 Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included 2021-10-06 08:56:01 -05:00
James E. Stine
b90d7b8083 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
Skylar Litz
a924e79e26 added delayed MIP signal 2021-10-04 18:23:31 -04:00
kipmacsaigoren
4a9dd49785 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-04 12:28:03 -05:00
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
a15068717b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:43:47 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
bbracker
07ff0940a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:30:49 -04:00
bbracker
a202c705cd checkpoint generator bugfixes 2021-10-03 00:30:04 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00