Rose Thompson
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13bb5d845b
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On the way to solving the store delay hazard.
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2023-12-13 10:39:01 -06:00 |
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Rose Thompson
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9348025727
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Cachefsm simplifications.
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2023-12-03 18:19:00 -06:00 |
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Rose Thompson
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3bef2a2361
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Better name for cache signals.
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2023-12-03 15:49:06 -06:00 |
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Rose Thompson
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025b04ae8b
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Minior cleanup.
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2023-11-29 19:44:59 -06:00 |
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Rose Thompson
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ab68a76e77
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LineDirty is either the Victim Way or the Flush way dirty, but never the hitway dirty. CBO instructions require hitway dirty. However we cannot mux hitway dirty into LineDirty wihtout creating a combinational loop so we need a separate port.
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2023-11-29 17:58:39 -06:00 |
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Rose Thompson
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80336493f5
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Cleaned up redundant ZICBOM/Z_SUPPORTED.
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2023-11-29 15:20:49 -06:00 |
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Rose Thompson
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0229df4a0f
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Oups. Introduced undetected bug into the cache's cbo insructions.
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2023-11-28 01:03:48 -06:00 |
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Rose Thompson
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337903d8dd
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More cache simplifications.
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2023-11-27 14:59:42 -06:00 |
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Rose Thompson
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08549446ef
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Reduced cache fsm complexity.
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2023-11-27 13:13:36 -06:00 |
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Rose Thompson
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c3da4c3c31
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Clarified names in cacheway.
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2023-11-27 12:56:11 -06:00 |
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Rose Thompson
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d7ef490c12
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Sutble bug in the cacheway logic for cacheline invalidation.
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2023-11-27 01:27:09 -06:00 |
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Rose Thompson
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58d89cc347
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-11-21 10:48:05 -06:00 |
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David Harris
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f89fd8a7fe
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removed unused cache signals
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2023-11-20 23:16:35 -08:00 |
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Rose Thompson
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1acc3951c8
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More simplifications.
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2023-11-21 00:19:24 -06:00 |
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Rose Thompson
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1d811b085c
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More cleanup.
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2023-11-21 00:14:59 -06:00 |
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Rose Thompson
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d2a747bf3d
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cleanup.
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2023-11-20 23:59:40 -06:00 |
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Rose Thompson
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70eb110a9c
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More optimizations to simplify cmo logic.
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2023-11-20 22:13:31 -06:00 |
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Rose Thompson
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52ac07ce8d
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Removed the CMO_WRITEBACK state from the cache and unused signals.
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2023-11-20 20:56:30 -06:00 |
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Rose Thompson
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667fe035c0
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Simplified CMO.Zero fsm implementation slightly.
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2023-11-20 17:01:43 -06:00 |
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Rose Thompson
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23e05cb8b2
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Finally have the cbo way muxing controls reduced to something sane.
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2023-11-20 11:28:03 -06:00 |
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Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
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David Harris
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1f2899de14
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Modified rams to take USE_SRAM rather than P to facilitate synthesis
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2023-11-03 05:44:13 -07:00 |
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Rose Thompson
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dce3c85105
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Progress.
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2023-10-27 16:31:22 -05:00 |
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David Harris
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6e7c0547a1
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Modified log2 coding to avoid synthesis warning
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2023-10-19 11:16:02 -07:00 |
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Ross Thompson
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11a3fd9314
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Slight modification to cachefsm.
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2023-09-05 14:07:58 -05:00 |
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Ross Thompson
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85ba53eeaf
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Merge pull request #406 from magpyed/cachesim_fix
Properly gate LRUWriteEn with ~FlushStage
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2023-09-05 11:10:58 -05:00 |
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Limnanthes Serafini
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6c78942685
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Properly gate LRUWriteEn with ~FlushStage
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2023-09-01 23:31:02 -07:00 |
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David Harris
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e75ceb044f
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Improved tlb and controller coverage; fixed exclusions on broken lines
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2023-08-31 00:27:47 -07:00 |
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Ross Thompson
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99455ad851
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Fixed minor performance bug with CBOZ.
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2023-08-24 17:08:20 -05:00 |
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Ross Thompson
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914b6f9734
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Now have CBOZ instructions working!
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2023-08-24 16:47:35 -05:00 |
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Ross Thompson
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c2a9fbb1fc
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Fixed bug with the cbo.inval clearing already cleared lines.
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2023-08-21 17:51:51 -05:00 |
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Ross Thompson
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05d590b0b9
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Fixed issue when with flush miss.
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2023-08-18 16:36:13 -05:00 |
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Ross Thompson
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fc3fccafe9
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Now we have invalidate, clean, and flush working.
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2023-08-18 16:32:22 -05:00 |
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Ross Thompson
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5c408454b8
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Might have working cbo clean and flush instructions.
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2023-08-18 14:48:21 -05:00 |
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Ross Thompson
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21129dde71
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Fixed cbo instruction decode.
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2023-08-18 11:32:30 -05:00 |
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Ross Thompson
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072126b967
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Found first bug in CMO implementation.
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2023-08-17 16:57:54 -05:00 |
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Ross Thompson
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f9df1fda23
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CMOZ now implemented in the D cache.
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2023-08-17 12:46:40 -05:00 |
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Ross Thompson
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624b3e3ab2
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Added clean and flush to cache fsm.
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2023-08-16 14:23:56 -05:00 |
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Ross Thompson
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5281077531
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More progress towards cmo.
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2023-08-15 18:17:15 -05:00 |
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Ross Thompson
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9f37fef145
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The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush.
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2023-08-14 16:39:18 -05:00 |
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Ross Thompson
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0eac74ac7b
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Initial CMO implementation. Just adds control signals into the L1 caches.
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2023-08-14 15:43:12 -05:00 |
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Ross Thompson
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7a196d3fa7
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Cache cleanup.
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2023-07-31 14:12:53 -05:00 |
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Ross Thompson
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d04d2afed2
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Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
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2023-07-21 13:06:27 -05:00 |
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Ross Thompson
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50bc679fef
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Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.
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2023-07-14 16:31:44 -05:00 |
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Ross Thompson
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38f32805ae
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Created separate temporary testbench for xcelium.
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2023-07-11 15:07:33 -05:00 |
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Ross Thompson
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85567841eb
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Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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Ross Thompson
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75b5c23edd
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Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
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2023-06-15 14:05:44 -05:00 |
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Ross Thompson
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009d8966e9
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Got the srams parameterized correctly now.
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2023-06-15 13:42:24 -05:00 |
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Ross Thompson
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b8a243827b
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Found a whole bunch of files still using the old `define configurations.
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2023-06-15 13:09:07 -05:00 |
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Harshini Srinath
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570a628198
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Update subcachelineread.sv
Code clean up
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2023-06-09 08:50:51 -07:00 |
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