Jacob Pease
11ca2567b8
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
bd07a60c07
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
6fc10adc25
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
Rose Thompson
5a6e32576d
Fixed the reset bug in wallyTracer.
2024-07-24 13:32:46 -05:00
Rose Thompson
13db14db6b
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
c11036358a
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
35efbd6a54
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
02f108345a
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
David Harris
f5f8a6c50c
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
David Harris
29bd6a30ab
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-15 04:27:59 -07:00
David Harris
459eaaef6a
Initial effort to make testbench_fp compatible with Verilator without breaking Questa
2024-07-14 20:08:33 -07:00
Rose Thompson
c53ea43ef9
Merge pull request #880 from davidharrishmc/dev
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wsim elf handling and RV64GCK lockstep support
2024-07-14 11:40:30 -05:00
David Harris
26d4fbcc19
Switched ImperasDV to RV64GCK model to support crypto (issue #872 )
2024-07-13 21:42:14 -07:00
Rose Thompson
f83e6cf771
Fixed issue #874 .
2024-07-08 14:48:52 -05:00
David Harris
84c687080d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-05 21:42:26 -07:00
David Harris
9f5e7b8653
Merge pull request #851 from kevindkim723/intdivb
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Reduce Bit widths for IDIV on FPU
2024-07-05 21:42:19 -07:00
David Harris
9279b2d56a
Added imperas configuration for Lee
2024-07-05 09:13:18 -07:00
David Harris
775930ae4f
Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test
2024-07-04 07:36:56 -07:00
David Harris
8645441d00
Testbench automatically creates memfile, label, addr files if they are out of date or missing
2024-07-03 16:52:16 -07:00
David Harris
a2fb6a21c5
Removed testbench-imperas now that wsim supports lockstep and single ELF files
2024-07-03 06:25:32 -07:00
David Harris
e72c8b8e09
Watchdog timeout on buildroot boot is a halting criteria
2024-07-02 14:22:51 -07:00
David Harris
38b0c10f9b
Updated wallyTracer to be compatible with VCS
2024-07-02 04:47:53 -07:00
David Harris
bf9fdcf9f9
Cleaned up lint errors in testbench_fp; still not working in Verilator because readvectors receives the wrong unit, fmt, opctrl
2024-06-27 04:26:56 -07:00
Jordan Carlin
784151e165
Fix testbench_fp to use F_SUPPORTED, not S_SUPPORTED
2024-06-26 22:29:00 -07:00
Jordan Carlin
221f710baf
Use QUESTA as flag for
2024-06-26 21:18:40 -07:00
Kevin Kim
4877633977
lint fixes tests vh
2024-06-21 22:16:09 -07:00
Kevin Kim
19f0cf7a35
putting back tests in tests vh
2024-06-21 21:51:44 -07:00
Kevin Kim
00bf3faa9c
changed intdivb width
2024-06-21 21:31:19 -07:00
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS
2024-06-21 15:17:59 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
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Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Rose Thompson
e1fc44a5bf
Merge pull request #849 from davidharrishmc/dev
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lint cleanup and divider optimization
2024-06-20 09:04:19 -07:00
David Harris
d8d94eeafa
Merge pull request #808 from jordancarlin/main
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Update riscv-arch-test
2024-06-20 08:43:41 -07:00
Jordan Carlin
90f5a4ef48
Only run fmsub_b15 for f_fma test
2024-06-20 07:48:33 -07:00
David Harris
25780f53ce
Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now.
2024-06-20 00:57:58 -07:00
Ross Thompson
d368f2e77e
Removed *** from testbench.
2024-06-19 13:51:37 -07:00
Ross Thompson
5e5ca0809f
Removed more *** from lsu and updated assertions for dtim.
2024-06-19 10:52:51 -07:00
Jordan Carlin
156bfc0387
Update f_fma tests to use smaller files from riscv-arch-test
2024-06-18 23:38:03 -07:00
Jordan Carlin
d58b454a8b
Finish switching Zfa to use riscv-arch-test
2024-06-18 23:31:37 -07:00
Jordan Carlin
955f5d831f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-18 22:39:05 -07:00
David Harris
ecae1100f6
Lint cleanup
2024-06-18 05:49:49 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
312c9c9f55
Updated logger to new IClass signal name
2024-06-12 07:24:05 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Jordan Carlin
c560a0ae8f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-01 23:22:30 -07:00
Rose Thompson
48fd365b9d
Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.
2024-05-28 13:00:17 -05:00
Rose Thompson
92ee56c1a1
Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
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testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Jordan Carlin
6f79dca9c4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-27 12:29:24 -07:00
