Ross Thompson
654c4d1148
simplified uncore's name for HWDATA.
2022-03-10 18:17:44 -06:00
Ross Thompson
1aa87c9f3a
Moved subwordwrite to lsu directory.
2022-03-10 18:15:25 -06:00
Ross Thompson
d0cf41dbe4
Simplified byte write enable logic.
2022-03-10 18:13:35 -06:00
Ross Thompson
396c97fc36
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35
Progress on the path to getting all configs working with byte write enables.
2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
David Harris
bc2b757952
bit write update
2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33
Refactored SRAM bit write enable
2022-03-09 17:49:28 +00:00
David Harris
89e0830883
Updated testbench to read expected flags
2022-03-09 13:58:17 +00:00
Ross Thompson
95bb4cc8a8
Minor cleanup to interlockfsm.
2022-03-08 23:38:58 -06:00
Ross Thompson
9b113149b6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-08 18:05:35 -06:00
Ross Thompson
0310fe858f
Comments.
2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee
Marked signals for name changes.
2022-03-08 17:41:02 -06:00
David Harris
00908132e6
Added more test cases and rounding modes to fma test generator
2022-03-08 23:29:29 +00:00
David Harris
8fa6a85af2
fixed setup.sh merge conflict
2022-03-08 23:21:06 +00:00
David Harris
c8f2dce026
fma16_testgen.c test cases
2022-03-08 23:18:18 +00:00
Ross Thompson
3ec32d7ce8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4
Added parameter to spillsupport.
2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
bbracker
742e8d98cd
fix up PLIC and UART checkpointing
2022-03-07 23:48:47 -08:00
bbracker
92e1583db5
change testbench-linux.sv to use new shared location of disassembly files
2022-03-07 20:04:08 -08:00
David Harris
7391c6d338
Checked in fma16_template.v
2022-03-06 13:29:35 +00:00
David Harris
e4d18f1808
removed more old 64priv tests
2022-03-04 03:57:19 +00:00
bbracker
41c75dc89d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:12:00 +00:00
bbracker
c3e59ae2df
comment out nonfunctioning CSR-PERMISSIONS-M test
2022-03-04 00:11:55 +00:00
David Harris
a50f1a4424
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:07:34 +00:00
David Harris
2cea3349ad
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
bbracker
d645666fe7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:06:27 +00:00
bbracker
79ff8d3c80
remove imperas32p tests
2022-03-04 00:06:18 +00:00
David Harris
6431ad4a8b
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
2022-03-03 15:38:08 +00:00
David Harris
f76e396255
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-02 23:47:16 +00:00
David Harris
8e83aaeced
fma file fixes
2022-03-02 23:47:01 +00:00
bbracker
87aad1d953
fix peripheral test and add it to regression
2022-03-02 23:44:39 +00:00
bbracker
11423d1d17
but apparently QEMU doesn't show UXL in SSTATUS
2022-03-02 22:44:19 +00:00
bbracker
6d7bc928af
update SXL UXL bits in MSTATUS to match new QEMU trace
2022-03-02 22:15:57 +00:00
bbracker
e9e827c83e
add CSRs to waveview
2022-03-02 18:31:10 +00:00
bbracker
4fe35aadf2
add rv32a tests to regression
2022-03-02 17:54:55 +00:00
bbracker
7d7a4fefb3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-02 17:46:40 +00:00
David Harris
c543fedc60
removed imperas-riscv-tests
2022-03-02 17:28:20 +00:00
bbracker
b6031bb15f
fix buildroot checkpointing and add it back to regression
2022-03-02 16:00:19 +00:00
bbracker
29179c6787
add LRSC test and add wally64a to regression
2022-03-02 07:09:37 +00:00
David Harris
0ecfff7e3a
FMA project ready to start
2022-03-01 20:58:08 +00:00
bbracker
d2fa5fa645
buildroot graphical sim bugfix
2022-03-01 03:24:23 +00:00
bbracker
a8e8cfb838
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
2022-03-01 03:11:43 +00:00
bbracker
d8ddda760b
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
2022-03-01 00:37:46 +00:00
David Harris
329fea9329
Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
2022-02-28 20:50:51 +00:00
David Harris
2ea93c4ac3
adrdecs comments
2022-02-28 20:33:41 +00:00
David Harris
2de31a15da
Modified address decoder for native access to CLINT
2022-02-28 19:13:14 +00:00
David Harris
3a43450ac9
hptw cleanup for synthesis
2022-02-28 05:54:34 +00:00
David Harris
f4be78ecc3
Created softfloat_demo showcasing how to do math with SoftFloat
2022-02-27 18:17:21 +00:00
David Harris
dbd73e8cfd
Moved regression work directories to regression/wkdir to reduce clutter
2022-02-27 17:35:09 +00:00
David Harris
3675a813c6
Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior
2022-02-27 17:23:33 +00:00
David Harris
62d62f9a9e
Moved FMA back into source tree to facilitate synthesis
2022-02-27 15:41:41 +00:00
David Harris
5b15e552c6
Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue
2022-02-27 15:12:10 +00:00
David Harris
c35a071203
Moved fma directory
2022-02-27 14:20:15 +00:00
David Harris
283a25e1a7
fma simulation infrastructure
2022-02-27 04:36:43 +00:00
David Harris
40bc380073
fma passing multiply vectors
2022-02-27 04:36:01 +00:00
David Harris
f29cc4b33f
simplified fma Makefile
2022-02-26 19:55:42 +00:00
David Harris
b2db58e982
Made softfloat.a a symlink
2022-02-26 19:53:04 +00:00
David Harris
a9f9cfa5b6
Added start of fma
2022-02-26 19:51:19 +00:00
David Harris
ff674b695c
Moved Softfloat / TestFloat
2022-02-26 19:17:32 +00:00
Ross Thompson
730fdb029a
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
6f53f7943f
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
19ec874641
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
15f6871a8d
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
834b308ed6
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
ea29291024
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-22 14:45:53 -06:00
Ross Thompson
971dd494f6
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
bbracker
2322e66f9f
fix lint bugs in PLIC and UART
2022-02-22 05:04:18 +00:00
bbracker
ac114e1c6d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-22 04:27:50 +00:00
bbracker
202bd2f8f8
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
bbracker
c26526c9f3
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
3ba70b74d6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 12:46:22 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
ushakya22
5f916d17d2
Moved order of reading a, b, and result from test vectors file so that result
...
matches up with inputs a and b
2022-02-21 17:28:11 +00:00
ushakya22
3abc2c0592
- created new testbench file instead of having it at the bottom of the srt file
...
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench
Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
2022-02-21 16:24:50 +00:00
ushakya22
1ea3e8120a
- Created exponent divsion module
...
- top module includes exponent module now
Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
2022-02-21 16:13:30 +00:00
ushakya22
3d5b407755
Changed Makefile to compile exptestgen instead of testgen
2022-02-21 16:08:45 +00:00
ushakya22
ec3fa45f86
reverted srt_standford back to original file pre modifications by Udeema
2022-02-21 16:08:09 +00:00
ushakya22
ed452aff5f
verilator lint for srt
2022-02-21 16:05:43 +00:00
ushakya22
a3a572fe5f
Created test vector generation file for exponent and mantissa division
2022-02-21 16:04:41 +00:00
Ross Thompson
5d9ad011d2
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Kip Macsai-Goren
04892c5d38
added scratch register tests for 64 and 32 bits
2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
d852e8a5c1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-21 00:34:54 +00:00
Ross Thompson
a60332b455
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
324efa7d42
added 32 bit pma tests to regression even though they've been working fo a while
2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
dcb5d0f6a9
Added misa test for both 32 and 64 bits
2022-02-18 19:41:50 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
