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Minor cleanup to interlockfsm.

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This commit is contained in:
Ross Thompson 2022-03-08 23:38:58 -06:00
parent 9b113149b6
commit 95bb4cc8a8
2 changed files with 7 additions and 5 deletions
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6
pipelined/src/lsu/interlockfsm.sv
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@ -44,7 +44,7 @@ module interlockfsm(
input logic DCacheStallM,
output logic InterlockStall,
output logic SelReplayCPURequest,
output logic SelReplayMemE,
output logic SelHPTW,
output logic IgnoreRequestTLB,
output logic IgnoreRequestTrapM);
@ -122,7 +122,9 @@ module interlockfsm(
endcase
end
assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY);
assign SelReplayMemE = (InterlockCurrState == STATE_T0_REPLAY & DCacheStallM) |
(InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) |
(InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF);
assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM));

6
pipelined/src/lsu/lsuvirtmen.sv
View File

@ -73,7 +73,7 @@ module lsuvirtmem(
logic [`PA_BITS-1:0] HPTWAdr;
logic [1:0] HPTWRW;
logic [2:0] HPTWSize;
logic SelReplayCPURequest;
logic SelReplayMemE;
logic [11:0] PreLSUAdrE;
logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
@ -85,7 +85,7 @@ module lsuvirtmem(
interlockfsm interlockfsm (
.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF,
.DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
.InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
.InterlockStall, .SelReplayMemE, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
hptw hptw(
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
@ -104,7 +104,7 @@ module lsuvirtmem(
if(`HPTW_WRITES_SUPPORTED)
mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM);
else assign LSUWriteDataM = WriteDataM;
mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache.
mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayMemE, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache.
// always block interrupts when using the hardware page table walker.
assign CPUBusy = StallW & ~SelHPTW;