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fix lint bugs in PLIC and UART

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bbracker 2022-02-22 05:04:18 +00:00
parent ac114e1c6d
commit 2322e66f9f
2 changed files with 4 additions and 4 deletions
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6
pipelined/src/uncore/plic.sv
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@ -113,7 +113,7 @@ module plic (
24'h002004: intEn[N:32] <= #1 Din[31:0];
`endif
24'h200000: intThreshold[2:0] <= #1 Din[2:0];
24'h200004: intInProgress <= #1 intInProgress & ~(4'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
24'h200004: intInProgress <= #1 intInProgress & ~(`PLIC_NUM_SRC'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
endcase
// reading
if (memread)
@ -132,7 +132,7 @@ module plic (
24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]};
24'h200004: begin
Dout <= #1 {26'b0,intClaim};
intInProgress <= #1 intInProgress | (4'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
intInProgress <= #1 intInProgress | (`PLIC_NUM_SRC'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
end
default: Dout <= #1 32'h0; // invalid access
endcase
@ -155,7 +155,7 @@ module plic (
// pending updates
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress
~({4{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read
~({N{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read
flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
// pending array - indexed by priority_lvl x source_ID

2
pipelined/src/uncore/uartPC16550D.sv
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@ -283,7 +283,7 @@ module uartPC16550D(
2'b10: rxdata9 = {1'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8]}; // 7-bit
2'b11: rxdata9 = { rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8], rxshiftreg[9]}; // 8-bit
endcase
assign rxdata = LCR[3] ? rxdata9[8:0] : rxdata9[8:1]; // discard parity bit
assign rxdata = LCR[3] ? rxdata9[7:0] : rxdata9[8:1]; // discard parity bit
// ERROR CONDITIONS
assign rxparity = ^rxdata;