mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
simplified uncore's name for HWDATA.
This commit is contained in:
parent
1aa87c9f3a
commit
654c4d1148
@ -38,7 +38,7 @@ module uncore (
|
||||
input logic HCLK, HRESETn,
|
||||
input logic TIMECLK,
|
||||
input logic [31:0] HADDR,
|
||||
input logic [`AHBW-1:0] HWDATAIN,
|
||||
input logic [`AHBW-1:0] HWDATA,
|
||||
input logic HWRITE,
|
||||
input logic [2:0] HSIZE,
|
||||
input logic [2:0] HBURST,
|
||||
@ -68,7 +68,6 @@ module uncore (
|
||||
output logic [63:0] MTIME_CLINT
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] HWDATA;
|
||||
logic [`XLEN-1:0] HREADRam, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC;
|
||||
|
||||
logic [8:0] HSELRegions;
|
||||
@ -90,10 +89,6 @@ module uncore (
|
||||
// unswizzle HSEL signals
|
||||
assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
|
||||
|
||||
// subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache.
|
||||
assign HWDATA = HWDATAIN;
|
||||
|
||||
|
||||
// generate
|
||||
// on-chip RAM
|
||||
if (`RAM_SUPPORTED) begin : ram
|
||||
|
@ -92,7 +92,7 @@ module wallypipelinedsoc (
|
||||
);
|
||||
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
|
||||
.TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
|
||||
.HSELEXT,
|
||||
|
Loading…
Reference in New Issue
Block a user