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Ross Thompson 2022-03-08 18:05:25 -06:00
parent 75e93baaee
commit 0310fe858f
1 changed files with 3 additions and 0 deletions
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pipelined/src/lsu/lsu.sv
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@ -253,7 +253,10 @@ module lsu (
if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS. Only produces byte write enable
logic [`XLEN-1:0] ReadDataWordMaskedM;
// ** there is definitely a sww bug with memory mapped i/o. check wally64priv.
assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate
// *** consider moving this AND gate into the sww.
//assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address.
subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]),
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM));