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Progress on the path to getting all configs working with byte write enables.

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This commit is contained in:
Ross Thompson 2022-03-10 17:02:52 -06:00
parent 67ef46ea92
commit d8e71e8e35
3 changed files with 48 additions and 24 deletions
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13
pipelined/src/lsu/lsu.sv
View File

@ -253,18 +253,11 @@ module lsu (
end
end
if(1) begin // *** always, not just with no MEM_BUS. Only produces byte write enable
logic [`XLEN-1:0] ReadDataWordMaskedM;
// ** there is definitely a sww bug with memory mapped i/o. check wally64priv.
//assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate
assign ReadDataWordMaskedM = '0; // AND-gate
// *** consider moving this AND gate into the sww.
//assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address.
subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]),
if(1) begin
subwordwrite subwordwrite(.HRDATA('0), .HADDRD(LSUPAdrM[2:0]),
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWEN(FinalByteWENM));
end else
assign FinalWriteDataM = FinalAMOWriteDataM;
end
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
.Funct3M(LSUFunct3M), .ReadDataM);

48
pipelined/src/uncore/ram.sv
View File

@ -38,6 +38,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
input logic HREADY,
input logic [1:0] HTRANS,
input logic [`XLEN-1:0] HWDATA,
input logic [3:0] HSIZED,
output logic [`XLEN-1:0] HREADRam,
output logic HRESPRam, HREADYRam
);
@ -53,6 +54,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
logic initTrans;
logic memwrite;
logic [3:0] busycount;
logic [`XLEN/8-1:0] ByteMaskM;
if(`FPGA) begin:ram
initial begin
@ -104,6 +106,33 @@ module ram #(parameter BASE=0, RANGE = 65535) (
end // initial begin
end // if (FPGA)
if(`XLEN == 64) begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[A[2:0]] = 1; end // sb
2'b01: case (A[2:1])
2'b00: ByteMaskM = 8'b0000_0011;
2'b01: ByteMaskM = 8'b0000_1100;
2'b10: ByteMaskM = 8'b0011_0000;
2'b11: ByteMaskM = 8'b1100_0000;
endcase
2'b10: if (A[2]) ByteMaskM = 8'b11110000;
else ByteMaskM = 8'b00001111;
2'b11: ByteMaskM = 8'b1111_1111;
endcase
end
end else begin
always_comb begin
case(HSIZED[1:0])
2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[A[1:0]] = 1; end // sb
2'b01: if (A[1]) ByteMaskM = 4'b1100;
else ByteMaskM = 4'b0011;
2'b10: ByteMaskM = 4'b1111;
default: ByteMaskM = 4'b1111;
endcase
end
end
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
// *** this seems like a weird way to use reset
@ -148,17 +177,24 @@ module ram #(parameter BASE=0, RANGE = 65535) (
-----/\----- EXCLUDED -----/\----- */
/* verilator lint_off WIDTH */
genvar index;
always_ff @(posedge HCLK)
HWADDR <= #1 A;
if (`XLEN == 64) begin:ramrw
always_ff @(posedge HCLK) begin
HWADDR <= #1 A;
always_ff @(posedge HCLK)
HREADRam0 <= #1 RAM[A[31:3]];
if (memwrite & risingHREADYRam) RAM[HWADDR[31:3]] <= #1 HWDATA;
for(index = 0; index < `XLEN/8; index++) begin
always_ff @(posedge HCLK) begin
if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:3]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index];
end
end
end else begin
always_ff @(posedge HCLK) begin:ramrw
HWADDR <= #1 A;
always_ff @(posedge HCLK)
HREADRam0 <= #1 RAM[A[31:2]];
if (memwrite & risingHREADYRam) RAM[HWADDR[31:2]] <= #1 HWDATA;
for(index = 0; index < `XLEN/8; index++) begin
always_ff @(posedge HCLK) begin:ramrw
if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:2]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index];
end
end
end
/* verilator lint_on WIDTH */

11
pipelined/src/uncore/uncore.sv
View File

@ -91,12 +91,7 @@ module uncore (
assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
// subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache.
if(0)
subwordwrite sww(
.HRDATA,
.HADDRD, .HSIZED,
.HWDATAIN, .HWDATA, .ByteWEN());
else assign HWDATA = HWDATAIN;
assign HWDATA = HWDATAIN;
// generate
@ -106,7 +101,7 @@ module uncore (
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK, .HRESETn,
.HSELRam, .HADDR,
.HWRITE, .HREADY,
.HWRITE, .HREADY, .HSIZED,
.HTRANS, .HWDATA, .HREADRam,
.HRESPRam, .HREADYRam);
end
@ -116,7 +111,7 @@ module uncore (
bootrom(
.HCLK, .HRESETn,
.HSELRam(HSELBootRom), .HADDR,
.HWRITE, .HREADY, .HTRANS,
.HWRITE, .HREADY, .HTRANS, .HSIZED,
.HWDATA,
.HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
end