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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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bbracker 2022-02-22 04:27:50 +00:00
commit ac114e1c6d
35 changed files with 7439 additions and 1967 deletions
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21
linux/buildroot-scripts/Makefile Normal file
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@ -0,0 +1,21 @@
all:
make disassemble
make generate
generate:
# generating device tree binary
dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb
disassemble:
mkdir ${RISCV}/buildroot/output/images/disassembly
# fw_jump
riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/fw_jump.elf >> ${RISCV}/buildroot/output/images/disassembly/fw_jump.objdump
# vmlinux
riscv64-unknown-elf-objdump -D ${RISCV}/buildroot/output/images/vmlinux >> ${RISCV}/buildroot/output/images/disassembly/vmlinux.objdump
# filesystem
mkdir ${RISCV}/buildroot/output/images/disassembly/rootfs
-cd ${RISCV}/buildroot/output/images/disassembly/rootfs; cpio -idv < ../../rootfs.cpio
clean:
rm ${RISCV}/buildroot/output/images/wally-virt.dtb
rm -rf ${RISCV}/buildroot/output/images/disassembly

2
pipelined/src/ifu/ifu.sv
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@ -249,6 +249,8 @@ module ifu (
assign PrivilegedChangePCM = RetM | TrapM;
// *** look at moves pcmux2 and pcmux3 to generates as they are needed only on supporting caches and
// privilege instructions respectively.
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));

6
pipelined/src/lsu/atomic.sv
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@ -34,7 +34,7 @@ module atomic (
input logic clk,
input logic reset, FlushW, CPUBusy,
input logic [`XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] WriteDataM,
input logic [`XLEN-1:0] LSUWriteDataM,
input logic [`PA_BITS-1:0] LSUPAdrM,
input logic [6:0] LSUFunct7M,
input logic [2:0] LSUFunct3M,
@ -49,9 +49,9 @@ module atomic (
logic [`XLEN-1:0] AMOResult;
logic MemReadM;
amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
.result(AMOResult));
mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
.SquashSCW, .LSURWM);

47
pipelined/src/lsu/lsu.sv
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@ -103,7 +103,8 @@ module lsu (
logic BusCommittedM, DCacheCommittedM;
logic LSUBusWriteCrit;
logic DataDAPageFaultM;
logic [`XLEN-1:0] LSUWriteDataM;
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
assign IEUAdrExtM = {2'b00, IEUAdrM};
assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
@ -118,8 +119,8 @@ module lsu (
.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
.TrapM, .DCacheStallM, .SATP_REGW, .PCF,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
.ReadDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM,
.IEUAdrExtM, .PTE, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE,
.ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
.IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE,
.LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW,
.IgnoreRequestTLB, .IgnoreRequestTrapM);
@ -129,6 +130,7 @@ module lsu (
assign LSUAdrE = PreLSUAdrE; assign PreLSUAdrE = IEUAdrE[11:0];
assign PreLSUPAdrM = IEUAdrExtM[`PA_BITS-1:0];
assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
assign LSUWriteDataM = WriteDataM;
end
// CommittedM tells the CPU's privilege unit the current instruction
@ -140,10 +142,11 @@ module lsu (
// MMU and Misalignment fault logic required if privileged unit exists
if(`ZICSR_SUPPORTED == 1) begin : dmmu
logic DisableTranslation;
assign DisableTranslation = SelHPTW | FlushDCacheM;
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(SelHPTW | FlushDCacheM),
.PrivilegeModeW, .DisableTranslation,
.PAdr(PreLSUPAdrM),
.VAdr(IEUAdrM),
.Size(LSUFunct3M[1:0]),
@ -158,7 +161,9 @@ module lsu (
.InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.DAPageFault(DataDAPageFaultM),
.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), // **** change this to just use PreLSURWM
// *** should use LSURWM as this is includes the lr/sc squash. However this introduces a combo loop
// from squash, depends on LSUPAdrM, depends on TLBHit, depends on these *AccessM inputs.
.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),
.WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
@ -173,10 +178,11 @@ module lsu (
// Memory System
// Either Data Cache or Data Tightly Integrated Memory or just bus interface
/////////////////////////////////////////////////////////////////////////////////////////////
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM, PostSWWWriteDataM;
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
logic [`XLEN-1:0] ReadDataWordM;
logic [`XLEN-1:0] ReadDataWordMuxM;
logic IgnoreRequest;
logic SelUncachedAdr;
assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM;
if (`DMEM == `MEM_TIM) begin : dtim
@ -184,7 +190,7 @@ module lsu (
.ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
.ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM,
.DCacheMiss, .DCacheAccess);
assign SelUncachedAdr = '0; // value does not matter.
end else begin : bus
localparam integer WORDSPERLINE = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS/`XLEN : 1;
localparam integer LINELEN = (`DMEM == `MEM_CACHE) ? `DCACHE_LINELENINBITS : `XLEN;
@ -199,7 +205,6 @@ module lsu (
logic [`PA_BITS-1:0] WordOffsetAddr;
logic SelBus;
logic [LOGWPL-1:0] WordCount;
logic SelUncachedAdr;
busdp #(WORDSPERLINE, LINELEN, LOGWPL, 1) busdp(
.clk, .reset,
@ -212,10 +217,13 @@ module lsu (
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheBusWriteData[`XLEN-1:0]),
.s(SelUncachedAdr), .y(ReadDataWordMuxM));
mux2 #(`XLEN) lsubushwdatamux( .d0(ReadDataWordM), .d1(FinalWriteDataM),
mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM),
.s(SelUncachedAdr), .y(LSUBusHWDATA));
assign WordOffsetAddr = LSUBusWriteCrit ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM;
mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM),
.d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit),
.y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset.
if(`DMEM == `MEM_CACHE) begin : dcache
logic [1:0] RW, Atomic;
assign RW = CacheableM ? LSURWM : 2'b00; // AND gate
@ -241,29 +249,28 @@ module lsu (
end
end
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
.Funct3M(LSUFunct3M), .ReadDataM);
if(`DMEM != `MEM_BUS) begin
logic [`XLEN-1:0] ReadDataWordMaskedM;
assign ReadDataWordMaskedM = CacheableM ? ReadDataWordM : '0; // AND-gate
assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate
subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]),
.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(PostSWWWriteDataM));
.HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM));
end else
assign PostSWWWriteDataM = FinalAMOWriteDataM;
assign FinalWriteDataM = FinalAMOWriteDataM;
assign FinalWriteDataM = SelHPTW ? PTE : PostSWWWriteDataM;
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
.Funct3M(LSUFunct3M), .ReadDataM);
/////////////////////////////////////////////////////////////////////////////////////////////
// Atomic operations
/////////////////////////////////////////////////////////////////////////////////////////////
// *** why does this need DTLBMissM?
if (`A_SUPPORTED) begin:atomic
atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM,
atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = WriteDataM;
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
end
endmodule

27
pipelined/src/lsu/lsuvirtmen.sv
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@ -47,19 +47,20 @@ module lsuvirtmem(
input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] PCF,
input logic [`XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] WriteDataM,
input logic [2:0] Funct3M,
output logic [2:0] LSUFunct3M,
input logic [6:0] Funct7M,
output logic [6:0] LSUFunct7M,
input logic [`XLEN-1:0] IEUAdrE,
input logic [`XLEN-1:0] IEUAdrM,
output logic [`XLEN-1:0] PTE,
output logic [`XLEN-1:0] LSUWriteDataM,
output logic [1:0] PageType,
output logic [1:0] PreLSURWM,
output logic [1:0] LSUAtomicM,
output logic [11:0] LSUAdrE,
output logic [`PA_BITS-1:0] PreLSUPAdrM,
input logic [`XLEN+1:0] IEUAdrExtM,
input logic [`XLEN+1:0] IEUAdrExtM, // *** can move internally.
output logic InterlockStall,
output logic CPUBusy,
@ -70,36 +71,40 @@ module lsuvirtmem(
logic AnyCPUReqM;
logic [`PA_BITS-1:0] HPTWAdr;
logic HPTWRead;
logic [1:0] HPTWRW;
logic [2:0] HPTWSize;
logic SelReplayCPURequest;
logic [11:0] PreLSUAdrE;
logic ITLBMissOrDAFaultF;
logic DTLBMissOrDAFaultM;
logic HPTWWrite;
logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
interlockfsm interlockfsm (
.clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF,
.DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
.InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
hptw hptw( // *** remove logic from (), mention this in style guide CH3
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, .MemRWM, .AtomicM,
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
.ITLBMissF(ITLBMissOrDAFaultF & ~TrapM), .DTLBMissM(DTLBMissOrDAFaultM & ~TrapM), // *** Fix me. *** I'm not sure ITLBMiss should be suppressed on TrapM.
.ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM,
.PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM),
.DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWWrite, .HPTWSize);
.DCacheStallM, .HPTWAdr, .HPTWRW, .HPTWSize);
// multiplex the outputs to LSU
mux2 #(2) rwmux(MemRWM, {HPTWRead, HPTWWrite}, SelHPTW, PreLSURWM);
mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw.
mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
if(`HPTW_WRITES_SUPPORTED)
mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM);
else assign LSUWriteDataM = WriteDataM;
mux2 #(12) replaymux(PreLSUAdrE, IEUAdrExtM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. *** redudant with mux in cache.
// always block interrupts when using the hardware page table walker.
assign CPUBusy = StallW & ~SelHPTW;

33
pipelined/src/mmu/hptw.sv
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@ -34,21 +34,21 @@ module hptw
(
input logic clk, reset,
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
input logic [`XLEN-1:0] PCF, // addresses to translate
input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate
input logic [1:0] MemRWM, AtomicM,
// system status
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP,
input logic [1:0] PrivilegeModeW,
(* mark_debug = "true" *) input logic ITLBMissF, DTLBMissM, // TLB Miss
(* mark_debug = "true" *) input logic ITLBMissOrDAFaultNoTrapF, DTLBMissOrDAFaultNoTrapM, // TLB Miss
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
input logic DCacheStallM, // stall from LSU
output logic [`XLEN-1:0] PTE, // page table entry to TLBs
output logic [1:0] PageType, // page type to TLBs
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
output logic [`PA_BITS-1:0] HPTWAdr,
output logic HPTWRead, // HPTW requesting to read memory
output logic HPTWWrite,
output logic [1:0] HPTWRW, // HPTW requesting to read memory
output logic [2:0] HPTWSize // 32 or 64 bit access.
);
@ -81,15 +81,15 @@ module hptw
// Extract bits from CSRs and inputs
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
assign TLBMiss = (DTLBMissM | ITLBMissF);
assign TLBMiss = (DTLBMissOrDAFaultNoTrapM | ITLBMissOrDAFaultNoTrapF);
// Determine which address to translate
assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF;
assign CurrentPPN = PTE[`PPN_BITS+9:10];
// State flops
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
assign PRegEn = HPTWRead & ~DCacheStallM;
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
assign PRegEn = HPTWRW[1] & ~DCacheStallM;
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache
@ -116,11 +116,11 @@ module hptw
logic SetDirty;
logic Dirty, Accessed;
assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE; // This will be HPTWReadPTE if not handling DAPageFault.
assign NextPTE = UpdatePTE ? {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]} : HPTWReadPTE;
flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
assign SaveHPTWAdr = WalkerState == L0_ADR;
assign SelHPTWWriteAdr = UpdatePTE | HPTWWrite;
mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); // HPTWAdr = HPTWReadAdr if not handling DAPageFault.
assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0];
mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr);
assign {Dirty, Accessed} = PTE[7:6];
@ -132,7 +132,7 @@ module hptw
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
// *** turn into module
// *** turn into module common with code in tlbcontrol.
if (`XLEN==64) begin:rv64
assign SV39Mode = (SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS] == `SV39);
// page fault if upper bits aren't all the same
@ -150,26 +150,25 @@ module hptw
assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid :
ImproperPrivilege | ~Executable | UpperBitsUnequalPageFault | Misaligned | ~Valid;
// hptw needs to know if there is a Dirty or Access fault occuring on this
// memory access. If there is the PTE needs to be updated seting Access
// and possibly also Dirty. Dirty is set if the operation is a store/amo.
// However any other fault should not cause the update.
assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault; // set to 0 if not handling DAPageFault.
assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault;
assign HPTWWrite = (WalkerState == UPDATE_PTE);
assign HPTWRW[0] = (WalkerState == UPDATE_PTE);
assign UpdatePTE = WalkerState == LEAF & DAPageFault;
end else begin // block: hptwwrites
assign NextPTE = HPTWReadPTE;
assign HPTWAdr = HPTWReadAdr;
assign DAPageFault = '0;
assign UpdatePTE = '0;
assign HPTWWrite = '0;
assign HPTWRW[0] = '0;
end
// Enable and select signals based on states
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
assign DTLBWriteM = (WalkerState == LEAF & ~DAPageFault) & DTLBWalk;
assign ITLBWriteF = (WalkerState == LEAF & ~DAPageFault) & ~DTLBWalk;

4
pipelined/srt/Makefile
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@ -3,5 +3,5 @@ all: sqrttestgen testgen
sqrttestgen: sqrttestgen.c
gcc sqrttestgen.c -lm -o sqrttestgen
testgen: testgen.c
gcc testgen.c -lm -o testgen
testgen: exptestgen.c
gcc exptestgen.c -lm -o exptestgen

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pipelined/srt/exptestgen Executable file
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121
pipelined/srt/exptestgen.c Normal file
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@ -0,0 +1,121 @@
/* testgen.c */
/* Written 2/19/2022 by David Harris
This program creates test vectors for mantissa and exponent components
of an IEEE floating point divider.
Builds upon program that creates test vectors for mantissa component only.
*/
/* #includes */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
/* Constants */
#define ENTRIES 17
#define RANDOM_VECS 500
// #define BIAS 1023 // Bias is for double precision
/* Prototypes */
void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa);
void printhex(FILE *fptr, double x);
double random_input(void);
double random_input_e(void);
/* Main */
void main(void)
{
FILE *fptr;
// e1 & e2 are exponents
// a & b are mantissas
// r_mantissa is result of mantissa divsion
// r_exp is result of exponent division
double a, b, r_mantissa, r_exp;
int e1, e2;
double mantissa[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625,
1.75, 1.875, 1.99999,
1.1, 1.2, 1.01, 1.001, 1.0001,
1/1.1, 1/1.5, 1/1.25, 1/1.125};
int exponent[ENTRIES] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17};
int i, j;
int bias = 1023;
if ((fptr = fopen("testvectors","w")) == NULL) {
fprintf(stderr, "Couldn't write testvectors file\n");
exit(1);
}
for (i=0; i<ENTRIES; i++) {
b = mantissa[i];
e2 = exponent[i] + bias;
for (j=0; j<ENTRIES; j++) {
a = mantissa[j];
e1 = exponent[j] + bias;
r_mantissa = a/b;
r_exp = e1 - e2 + bias;
output(fptr, e1, a, e2, b, r_exp, r_mantissa);
}
}
// for (i = 0; i< RANDOM_VECS; i++) {
// a = random_input();
// b = random_input();
// e1 = random_input_e() + BIAS; // make new random input function for exponents
// e2 = random_input_e() + BIAS;
// r_mantissa = a/b;
// r_exp = e1 - e2 + BIAS;
// output(fptr, e1, a, e2, b, r_exp, r_mantissa);
// }
fclose(fptr);
}
/* Functions */
void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa)
{
fprintf(fptr, "%03x", e1);
//printhex(fptr, e1, exp);
printhex(fptr, a);
fprintf(fptr, "_");
fprintf(fptr, "%03x", e2);
//printhex(fptr, e2, exp);
printhex(fptr, b);
fprintf(fptr, "_");
fprintf(fptr, "%03x", r_exp);
//printhex(fptr, r_exp, exp);
printhex(fptr, r_mantissa);
fprintf(fptr, "\n");
}
void printhex(FILE *fptr, double m)
{
int i, val, len;
len = 52;
while (m<1) m *= 2;
while (m>2) m /= 2;
for (i=0; i<len; i+=4) {
m = m - floor(m);
m = m * 16;
val = (int)(m)%16;
fprintf(fptr, "%x", val);
}
}
double random_input(void)
{
return 1.0 + rand()/32767.0;
}
double random_input_e(void)
{
return rand() % 300 + 1;
}

1
pipelined/srt/lint-srt
View File

@ -1 +1,2 @@
verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv

14
pipelined/srt/srt.sv
View File

@ -37,6 +37,8 @@ module srt #(parameter Nf=52) (
input logic Flush, // *** multiple pipe stages
// Floating Point Inputs
// later add exponents, signs, special cases
input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits
// end of floating point inputs
input logic [Nf-1:0] SrcXFrac, SrcYFrac,
input logic [`XLEN-1:0] SrcA, SrcB,
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
@ -45,6 +47,7 @@ module srt #(parameter Nf=52) (
input logic Int, // Choose integer inputss
input logic Sqrt, // perform square root, not divide
output logic [Nf-1:0] Quot, Rem, // *** later handle integers
output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision
output logic [3:0] Flags
);
@ -78,6 +81,9 @@ module srt #(parameter Nf=52) (
// Partial Product Generation
csa csa(WS, WC, Dsel, qp, WSA, WCA);
// Exponent division
exp exp(SrcXExpE, SrcYExpE, Exp);
srtpostproc postproc(rp, rm, Quot);
endmodule
@ -247,6 +253,14 @@ module csa #(parameter N=56) (
(in2[54:0] & in3[54:0]), cin};
endmodule
//////////////
// exponent //
//////////////
module exp(input [10:0] e1, e2,
output [10:0] e); // for double precision, exponent is 11 bits
assign e = (e1 - e2) + 11'd1023; // bias is hardcoded
endmodule
//////////////
// finaladd //
//////////////

92
pipelined/srt/srt_stanford.sv
View File

@ -14,49 +14,6 @@
`include "wally-config.vh"
// will also be used for integer division so keep in mind when naming modules/signals
/////////////////
// srt_divide //
////////////////
module srt_divide(input logic clk,
input logic req,
input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b
input logic [63:0] a, b, // input numbers
output logic [54:0] rp, rm,
output logic [10:0] expE);
// output logic from Unpackers
logic XSgnE, YSgnE, ZSgnE;
logic [10:0] XExpE, YExpE, ZExpE; // exponent
logic [52:0] XManE, YManE, ZManE;
logic XNormE;
logic XNaNE, YNaNE, ZNaNE;
logic XSNaNE, YSNaNE, ZSNaNE;
logic XDenormE, YDenormE, ZDenormE; // denormals
logic XZeroE, YZeroE, ZZeroE;
logic [10:0] BiasE; // currrently hardcoded, will probs be removed
logic XInfE, YInfE, ZInfE;
logic XExpMaxE; // says exponent is all ones, can ignore
// have Unpackers
// have mantissa divider
// exponent divider
// hopefully having the .* here works for unpacker --- nope it doesn't
unpack unpacking(a, b, 0, 1'b1, 0, XSgnE, YSgnE, ZSgnE, XExpE, YExpE, ZExpE, XManE, YManE, ZManE, XNormE,XNaNE, YNaNE, ZNaNE,XSNaNE, YSNaNE, ZSNaNE,XDenormE, YDenormE, ZDenormE,XZeroE, YZeroE, ZZeroE,BiasE,XInfE, YInfE, ZInfE,XExpMaxE);
srt srt(clk, req, XManE[51:0], YManE[51:0], rp, rm);
exp exp(XexpE, YExpE, expE);
endmodule
// exponent module
// first iteration
module exp(input [10:0] e1, e2,
output [10:0] e); // for a 64 bit number, exponent section is 11 bits
assign e = (e1 - e2) + 11'd1023; // bias is hardcoded
endmodule
/////////
// srt //
/////////
@ -84,12 +41,12 @@ module srt(input logic clk,
// When start is asserted, the inputs are loaded into the divider.
// Otherwise, the divisor is retained and the partial remainder
// is fed back for the next iteration.
mux2_special psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn);
flop_special psflop(clk, psn, ps);
mux2_special pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn);
flop_special pcflop(clk, pcn, pc);
mux2_special dmux(d, {4'b0001, b}, req, dn);
flop_special dflop(clk, dn, d);
mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn);
flop psflop(clk, psn, ps);
mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn);
flop pcflop(clk, pcn, pc);
mux2 dmux(d, {4'b0001, b}, req, dn);
flop dflop(clk, dn, d);
// Quotient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
@ -99,7 +56,7 @@ module srt(input logic clk,
// Divisor Selection logic
inv dinv(d, d_b);
mux3_special divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel);
mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel);
// Partial Product Generation
csa csa(ps, pc, dsel, qp, psa, pca);
@ -108,7 +65,7 @@ endmodule
//////////
// mux2 //
//////////
module mux2_special(input logic [55:0] in0, in1,
module mux2(input logic [55:0] in0, in1,
input logic sel,
output logic [55:0] out);
@ -118,7 +75,7 @@ endmodule
//////////
// flop //
//////////
module flop_special(clk, in, out);
module flop(clk, in, out);
input clk;
input [55:0] in;
output [55:0] out;
@ -204,9 +161,9 @@ module inv(input logic [55:0] in,
endmodule
//////////
// mux3_special //
// mux3 //
//////////
module mux3_special(in0, in1, in2, sel0, sel1, sel2, out);
module mux3(in0, in1, in2, sel0, sel1, sel2, out);
input [55:0] in0;
input [55:0] in1;
input [55:0] in2;
@ -316,24 +273,6 @@ module testbench;
logic [51:0] b;
logic [51:0] r;
logic [54:0] rp, rm; // positive quotient digits
//input logic [63:0] X, Y, Z, - numbers
//input logic FmtE, ---- format, 1 is for double precision, 0 is single
//input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide
// all variables are commented in fpu.sv
// output logic from Unpackers
logic XSgnE, YSgnE, ZSgnE;
logic [10:0] XExpE, YExpE, ZExpE; // exponent
logic [52:0] XManE, YManE, ZManE;
logic XNormE;
logic XNaNE, YNaNE, ZNaNE;
logic XSNaNE, YSNaNE, ZSNaNE;
logic XDenormE, YDenormE, ZDenormE; // denormals
logic XZeroE, YZeroE, ZZeroE;
logic [10:0] BiasE; // currrently hardcoded, will probs be removed
logic XInfE, YInfE, ZInfE;
logic XExpMaxE; // says exponent is all ones, can ignore
// Test parameters
parameter MEM_SIZE = 40000;
@ -350,15 +289,8 @@ module testbench;
logic [51:0] correctr, nextr;
integer testnum, errors;
// Unpackers
unpacking unpack(.X({12'b100010000010,a}), .Y({12'b100010000001,b}), .Z(0), .FmtE(1'b1), .FOpCtrlE(0), .*);
// Divider
srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(XManE[51:0]), .b(YManE[51:0]), .rp(rp),.rm(rm));
//srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(a), .b(b), .rp(rp),.rm(rm));
// Divider + unpacker
srt srt(clk, req, a, b, rp, rm);
// Final adder converts quotient digits to 2's complement & normalizes
finaladd finaladd(rp, rm, r);

73
pipelined/srt/testbench.sv
View File

@ -40,33 +40,66 @@ module testbench;
logic clk;
logic req;
logic done;
logic [51:0] a;
logic [51:0] b;
logic [51:0] r;
logic [63:0] a;
logic [63:0] b;
logic [63:0] result;
logic [51:0] r;
logic [54:0] rp, rm; // positive quotient digits
logic [10:0] e; // output exponent
// input logic for Unpacker
// input logic [63:0] X, Y, Z, - numbers
// input logic FmtE, ---- format, 1 is for double precision, 0 is single
// input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide
// all variables are commented in fpu.sv
// output logic from Unpacker
logic XSgnE, YSgnE, ZSgnE;
logic [10:0] XExpE, YExpE, ZExpE; // exponent
logic [52:0] XManE, YManE, ZManE;
logic XNormE;
logic XNaNE, YNaNE, ZNaNE;
logic XSNaNE, YSNaNE, ZSNaNE;
logic XDenormE, YDenormE, ZDenormE; // denormals
logic XZeroE, YZeroE, ZZeroE;
logic [10:0] BiasE; // currrently hardcoded, will probs be removed
logic XInfE, YInfE, ZInfE;
logic XExpMaxE; // says exponent is all ones, can ignore
// Test parameters
parameter MEM_SIZE = 40000;
parameter MEM_WIDTH = 52+52+52;
parameter MEM_SIZE = 60000;
parameter MEM_WIDTH = 64+64+64;
`define memr 51:0
`define memb 103:52
`define mema 155:104
`define memr 63:0
`define memb 127:64
`define mema 191:128
// Test logicisters
logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
// bit field of an array
logic [51:0] correctr, nextr, diffn, diffp;
logic [63:0] correctr, nextr, diffn, diffp;
integer testnum, errors;
// Unpacker
// Note: BiasE will probably get taken out eventually
unpacking unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
.XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
.XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
.XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
.XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE),
.XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE));
// Divider
srt #(52) srt(.clk, .Start(req),
.Stall(1'b0), .Flush(1'b0),
.SrcXFrac(a), .SrcYFrac(b),
.SrcXExpE(XExpE), .SrcYExpE(YExpE),
.SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]),
.SrcA('0), .SrcB('0), .Fmt(2'b00),
.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
.Quot(r), .Rem(), .Flags());
.Quot(r), .Rem(), .Exp(e), .Flags());
assign result = {1'b0, e, r};
// Counter
counter counter(clk, req, done);
@ -100,16 +133,18 @@ module testbench;
if (done)
begin
req <= #5 1;
diffp = correctr - r;
diffn = r - correctr;
diffp = correctr - result;
diffn = result - correctr;
if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
begin
errors = errors+1;
$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
$display("a = %h b = %h result = %h",a,b,correctr);
$display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp);
$display("at fail");
$display("failed\n");
$stop;
end
if (a === 52'hxxxxxxxxxxxxx)
if (a === 64'hxxxxxxxxxxxxxxxx)
begin
$display("%d Tests completed successfully", testnum);
$stop;
@ -119,12 +154,14 @@ module testbench;
begin
req <= #5 0;
correctr = nextr;
$display("pre increment");
testnum = testnum+1;
Vec = Tests[testnum];
$display("a = %h b = %h",a,b);
a = Vec[`mema];
a = Vec[`mema];
b = Vec[`memb];
Vec = Tests[testnum];
$display("a = %h b = %h result = %h",a,b,nextr);
nextr = Vec[`memr];
$display("after increment");
end
end

1078
pipelined/srt/testvectors
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11
pipelined/testbench/tests.vh
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@ -1478,7 +1478,10 @@ string imperas32f[] = '{
"rv64i_m/privilege/WALLY-PMA", "40A0",
"rv64i_m/privilege/WALLY-minfo-01", "40A0",
"rv64i_m/privilege/WALLY-CSR-permission-s-01", "50A0",
"rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0"
"rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0",
"rv64i_m/privilege/WALLY-misa-01", "40A0",
"rv64i_m/privilege/WALLY-scratch-01", "40A0",
"rv64i_m/privilege/WALLY-sscratch-s-01", "40A0"
};
string wally64periph[] = '{
@ -1540,9 +1543,13 @@ string wally32i[] = '{
`WALLYTEST,
"rv32i_m/privilege/WALLY-MMU-SV32", "4080",
"rv32i_m/privilege/WALLY-PMP", "4080",
"rv32i_m/privilege/WALLY-PMA", "4080",
"rv32i_m/privilege/WALLY-CSR-permission-s-01", "5080",
"rv32i_m/privilege/WALLY-CSR-permission-u-01", "5080",
"rv32i_m/privilege/WALLY-minfo-01", "4080"
"rv32i_m/privilege/WALLY-minfo-01", "4080",
"rv32i_m/privilege/WALLY-misa-01", "4080",
"rv32i_m/privilege/WALLY-scratch-01", "4080",
"rv32i_m/privilege/WALLY-sscratch-s-01", "4080"
};
string wally32periph[] = '{

5
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
View File

@ -32,7 +32,10 @@ rv32i_sc_tests = \
WALLY-PMP \
WALLY-CSR-permission-s-01 \
WALLY-CSR-permission-u-01 \
WALLY-minfo-01
WALLY-minfo-01 \
WALLY-misa-01 \
WALLY-scratch-01 \
WALLY-sscratch-s-01
target_tests_nosim = WALLY-PMA \

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output Normal file
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1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output Normal file
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1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output Normal file
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274
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S
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@ -34,161 +34,161 @@ s_file_begin:
GOTO_S_MODE 0x0, 0x0
# Attempt to write 0xbad to each of these CSRs and read the value back
# Attempt to write 0x111 to each of these CSRs and read the value back
# should result in an illegal instruction for the write and read, respectively
# High-bit versions storing the upper 32 bits of some CSRs for RV32
# WRITE_READ_CSR mstatush 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR menvcfgh 0xbad
# WRITE_READ_CSR mseccfgh 0xbad
WRITE_READ_CSR pmpcfg1 0xbad
WRITE_READ_CSR pmpcfg3 0xbad
WRITE_READ_CSR mcycleh 0xbad
WRITE_READ_CSR minstreth 0xbad
WRITE_READ_CSR mhpmcounter3h 0xbad
WRITE_READ_CSR mhpmcounter4h 0xbad
WRITE_READ_CSR mhpmcounter5h 0xbad
WRITE_READ_CSR mhpmcounter6h 0xbad
WRITE_READ_CSR mhpmcounter7h 0xbad
WRITE_READ_CSR mhpmcounter8h 0xbad
WRITE_READ_CSR mhpmcounter9h 0xbad
WRITE_READ_CSR mhpmcounter10h 0xbad
WRITE_READ_CSR mhpmcounter11h 0xbad
WRITE_READ_CSR mhpmcounter12h 0xbad
WRITE_READ_CSR mhpmcounter13h 0xbad
WRITE_READ_CSR mhpmcounter14h 0xbad
WRITE_READ_CSR mhpmcounter15h 0xbad
WRITE_READ_CSR mhpmcounter16h 0xbad
WRITE_READ_CSR mhpmcounter17h 0xbad
WRITE_READ_CSR mhpmcounter18h 0xbad
WRITE_READ_CSR mhpmcounter19h 0xbad
WRITE_READ_CSR mhpmcounter20h 0xbad
WRITE_READ_CSR mhpmcounter21h 0xbad
WRITE_READ_CSR mhpmcounter22h 0xbad
WRITE_READ_CSR mhpmcounter23h 0xbad
WRITE_READ_CSR mhpmcounter24h 0xbad
WRITE_READ_CSR mhpmcounter25h 0xbad
WRITE_READ_CSR mhpmcounter26h 0xbad
WRITE_READ_CSR mhpmcounter27h 0xbad
WRITE_READ_CSR mhpmcounter28h 0xbad
WRITE_READ_CSR mhpmcounter29h 0xbad
WRITE_READ_CSR mhpmcounter30h 0xbad
WRITE_READ_CSR mhpmcounter31h 0xbad
# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR menvcfgh 0x111
# WRITE_READ_CSR mseccfgh 0x111
WRITE_READ_CSR pmpcfg1 0x111
WRITE_READ_CSR pmpcfg3 0x111
WRITE_READ_CSR mcycleh 0x111
WRITE_READ_CSR minstreth 0x111
WRITE_READ_CSR mhpmcounter3h 0x111
WRITE_READ_CSR mhpmcounter4h 0x111
WRITE_READ_CSR mhpmcounter5h 0x111
WRITE_READ_CSR mhpmcounter6h 0x111
WRITE_READ_CSR mhpmcounter7h 0x111
WRITE_READ_CSR mhpmcounter8h 0x111
WRITE_READ_CSR mhpmcounter9h 0x111
WRITE_READ_CSR mhpmcounter10h 0x111
WRITE_READ_CSR mhpmcounter11h 0x111
WRITE_READ_CSR mhpmcounter12h 0x111
WRITE_READ_CSR mhpmcounter13h 0x111
WRITE_READ_CSR mhpmcounter14h 0x111
WRITE_READ_CSR mhpmcounter15h 0x111
WRITE_READ_CSR mhpmcounter16h 0x111
WRITE_READ_CSR mhpmcounter17h 0x111
WRITE_READ_CSR mhpmcounter18h 0x111
WRITE_READ_CSR mhpmcounter19h 0x111
WRITE_READ_CSR mhpmcounter20h 0x111
WRITE_READ_CSR mhpmcounter21h 0x111
WRITE_READ_CSR mhpmcounter22h 0x111
WRITE_READ_CSR mhpmcounter23h 0x111
WRITE_READ_CSR mhpmcounter24h 0x111
WRITE_READ_CSR mhpmcounter25h 0x111
WRITE_READ_CSR mhpmcounter26h 0x111
WRITE_READ_CSR mhpmcounter27h 0x111
WRITE_READ_CSR mhpmcounter28h 0x111
WRITE_READ_CSR mhpmcounter29h 0x111
WRITE_READ_CSR mhpmcounter30h 0x111
WRITE_READ_CSR mhpmcounter31h 0x111
# Machine information Registers
WRITE_READ_CSR mvendorid, 0xbad
WRITE_READ_CSR marchid, 0xbad
WRITE_READ_CSR mimpid, 0xbad
WRITE_READ_CSR mhartid, 0xbad
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mvendorid, 0x111
WRITE_READ_CSR marchid, 0x111
WRITE_READ_CSR mimpid, 0x111
WRITE_READ_CSR mhartid, 0x111
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0xbad
WRITE_READ_CSR misa, 0xbad
WRITE_READ_CSR medeleg, 0xbad
WRITE_READ_CSR mideleg, 0xbad
WRITE_READ_CSR mie, 0xbad
WRITE_READ_CSR mtvec, 0xbad
WRITE_READ_CSR mcounteren, 0xbad
WRITE_READ_CSR mstatus, 0x111
WRITE_READ_CSR misa, 0x111
WRITE_READ_CSR medeleg, 0x111
WRITE_READ_CSR mideleg, 0x111
WRITE_READ_CSR mie, 0x111
WRITE_READ_CSR mtvec, 0x111
WRITE_READ_CSR mcounteren, 0x111
# Machine Trap Handling
WRITE_READ_CSR mscratch, 0xbad
WRITE_READ_CSR mepc, 0xbad
WRITE_READ_CSR mcause, 0xbad
WRITE_READ_CSR mtval, 0xbad
WRITE_READ_CSR mip, 0xbad
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0xbad
WRITE_READ_CSR mscratch, 0x111
WRITE_READ_CSR mepc, 0x111
WRITE_READ_CSR mcause, 0x111
WRITE_READ_CSR mtval, 0x111
WRITE_READ_CSR mip, 0x111
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0x111
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0xbad
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0x111
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0xbad
WRITE_READ_CSR pmpcfg2, 0xbad # there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpcfg0, 0x111
WRITE_READ_CSR pmpcfg2, 0x111 # there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpaddr0, 0xbad
WRITE_READ_CSR pmpaddr1, 0xbad
WRITE_READ_CSR pmpaddr2, 0xbad
WRITE_READ_CSR pmpaddr3, 0xbad
WRITE_READ_CSR pmpaddr4, 0xbad
WRITE_READ_CSR pmpaddr5, 0xbad
WRITE_READ_CSR pmpaddr6, 0xbad
WRITE_READ_CSR pmpaddr7, 0xbad
WRITE_READ_CSR pmpaddr8, 0xbad
WRITE_READ_CSR pmpaddr9, 0xbad
WRITE_READ_CSR pmpaddr10, 0xbad
WRITE_READ_CSR pmpaddr11, 0xbad
WRITE_READ_CSR pmpaddr12, 0xbad
WRITE_READ_CSR pmpaddr13, 0xbad
WRITE_READ_CSR pmpaddr14, 0xbad
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
WRITE_READ_CSR pmpaddr0, 0x111
WRITE_READ_CSR pmpaddr1, 0x111
WRITE_READ_CSR pmpaddr2, 0x111
WRITE_READ_CSR pmpaddr3, 0x111
WRITE_READ_CSR pmpaddr4, 0x111
WRITE_READ_CSR pmpaddr5, 0x111
WRITE_READ_CSR pmpaddr6, 0x111
WRITE_READ_CSR pmpaddr7, 0x111
WRITE_READ_CSR pmpaddr8, 0x111
WRITE_READ_CSR pmpaddr9, 0x111
WRITE_READ_CSR pmpaddr10, 0x111
WRITE_READ_CSR pmpaddr11, 0x111
WRITE_READ_CSR pmpaddr12, 0x111
WRITE_READ_CSR pmpaddr13, 0x111
WRITE_READ_CSR pmpaddr14, 0x111
WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
# Machine Counter/Timers
WRITE_READ_CSR mcycle, 0xbad
WRITE_READ_CSR minstret, 0xbad
WRITE_READ_CSR mhpmcounter3, 0xbad
WRITE_READ_CSR mhpmcounter4, 0xbad
WRITE_READ_CSR mhpmcounter5, 0xbad
WRITE_READ_CSR mhpmcounter6, 0xbad
WRITE_READ_CSR mhpmcounter7, 0xbad
WRITE_READ_CSR mhpmcounter8, 0xbad
WRITE_READ_CSR mhpmcounter9, 0xbad
WRITE_READ_CSR mhpmcounter10, 0xbad
WRITE_READ_CSR mhpmcounter11, 0xbad
WRITE_READ_CSR mhpmcounter12, 0xbad
WRITE_READ_CSR mhpmcounter13, 0xbad
WRITE_READ_CSR mhpmcounter14, 0xbad
WRITE_READ_CSR mhpmcounter15, 0xbad
WRITE_READ_CSR mhpmcounter16, 0xbad
WRITE_READ_CSR mhpmcounter17, 0xbad
WRITE_READ_CSR mhpmcounter18, 0xbad
WRITE_READ_CSR mhpmcounter19, 0xbad
WRITE_READ_CSR mhpmcounter20, 0xbad
WRITE_READ_CSR mhpmcounter21, 0xbad
WRITE_READ_CSR mhpmcounter22, 0xbad
WRITE_READ_CSR mhpmcounter23, 0xbad
WRITE_READ_CSR mhpmcounter24, 0xbad
WRITE_READ_CSR mhpmcounter25, 0xbad
WRITE_READ_CSR mhpmcounter26, 0xbad
WRITE_READ_CSR mhpmcounter27, 0xbad
WRITE_READ_CSR mhpmcounter28, 0xbad
WRITE_READ_CSR mhpmcounter29, 0xbad
WRITE_READ_CSR mhpmcounter30, 0xbad
WRITE_READ_CSR mhpmcounter31, 0xbad
WRITE_READ_CSR mcycle, 0x111
WRITE_READ_CSR minstret, 0x111
WRITE_READ_CSR mhpmcounter3, 0x111
WRITE_READ_CSR mhpmcounter4, 0x111
WRITE_READ_CSR mhpmcounter5, 0x111
WRITE_READ_CSR mhpmcounter6, 0x111
WRITE_READ_CSR mhpmcounter7, 0x111
WRITE_READ_CSR mhpmcounter8, 0x111
WRITE_READ_CSR mhpmcounter9, 0x111
WRITE_READ_CSR mhpmcounter10, 0x111
WRITE_READ_CSR mhpmcounter11, 0x111
WRITE_READ_CSR mhpmcounter12, 0x111
WRITE_READ_CSR mhpmcounter13, 0x111
WRITE_READ_CSR mhpmcounter14, 0x111
WRITE_READ_CSR mhpmcounter15, 0x111
WRITE_READ_CSR mhpmcounter16, 0x111
WRITE_READ_CSR mhpmcounter17, 0x111
WRITE_READ_CSR mhpmcounter18, 0x111
WRITE_READ_CSR mhpmcounter19, 0x111
WRITE_READ_CSR mhpmcounter20, 0x111
WRITE_READ_CSR mhpmcounter21, 0x111
WRITE_READ_CSR mhpmcounter22, 0x111
WRITE_READ_CSR mhpmcounter23, 0x111
WRITE_READ_CSR mhpmcounter24, 0x111
WRITE_READ_CSR mhpmcounter25, 0x111
WRITE_READ_CSR mhpmcounter26, 0x111
WRITE_READ_CSR mhpmcounter27, 0x111
WRITE_READ_CSR mhpmcounter28, 0x111
WRITE_READ_CSR mhpmcounter29, 0x111
WRITE_READ_CSR mhpmcounter30, 0x111
WRITE_READ_CSR mhpmcounter31, 0x111
# Machine Counter Setup
WRITE_READ_CSR mcountinhibit, 0xbad
WRITE_READ_CSR mhpmevent3, 0xbad
WRITE_READ_CSR mhpmevent4, 0xbad
WRITE_READ_CSR mhpmevent5, 0xbad
WRITE_READ_CSR mhpmevent6, 0xbad
WRITE_READ_CSR mhpmevent7, 0xbad
WRITE_READ_CSR mhpmevent8, 0xbad
WRITE_READ_CSR mhpmevent9, 0xbad
WRITE_READ_CSR mhpmevent10, 0xbad
WRITE_READ_CSR mhpmevent11, 0xbad
WRITE_READ_CSR mhpmevent12, 0xbad
WRITE_READ_CSR mhpmevent13, 0xbad
WRITE_READ_CSR mhpmevent14, 0xbad
WRITE_READ_CSR mhpmevent15, 0xbad
WRITE_READ_CSR mhpmevent16, 0xbad
WRITE_READ_CSR mhpmevent17, 0xbad
WRITE_READ_CSR mhpmevent18, 0xbad
WRITE_READ_CSR mhpmevent19, 0xbad
WRITE_READ_CSR mhpmevent20, 0xbad
WRITE_READ_CSR mhpmevent21, 0xbad
WRITE_READ_CSR mhpmevent22, 0xbad
WRITE_READ_CSR mhpmevent23, 0xbad
WRITE_READ_CSR mhpmevent24, 0xbad
WRITE_READ_CSR mhpmevent25, 0xbad
WRITE_READ_CSR mhpmevent26, 0xbad
WRITE_READ_CSR mhpmevent27, 0xbad
WRITE_READ_CSR mhpmevent28, 0xbad
WRITE_READ_CSR mhpmevent29, 0xbad
WRITE_READ_CSR mhpmevent30, 0xbad
WRITE_READ_CSR mhpmevent31, 0xbad
WRITE_READ_CSR mcountinhibit, 0x111
WRITE_READ_CSR mhpmevent3, 0x111
WRITE_READ_CSR mhpmevent4, 0x111
WRITE_READ_CSR mhpmevent5, 0x111
WRITE_READ_CSR mhpmevent6, 0x111
WRITE_READ_CSR mhpmevent7, 0x111
WRITE_READ_CSR mhpmevent8, 0x111
WRITE_READ_CSR mhpmevent9, 0x111
WRITE_READ_CSR mhpmevent10, 0x111
WRITE_READ_CSR mhpmevent11, 0x111
WRITE_READ_CSR mhpmevent12, 0x111
WRITE_READ_CSR mhpmevent13, 0x111
WRITE_READ_CSR mhpmevent14, 0x111
WRITE_READ_CSR mhpmevent15, 0x111
WRITE_READ_CSR mhpmevent16, 0x111
WRITE_READ_CSR mhpmevent17, 0x111
WRITE_READ_CSR mhpmevent18, 0x111
WRITE_READ_CSR mhpmevent19, 0x111
WRITE_READ_CSR mhpmevent20, 0x111
WRITE_READ_CSR mhpmevent21, 0x111
WRITE_READ_CSR mhpmevent22, 0x111
WRITE_READ_CSR mhpmevent23, 0x111
WRITE_READ_CSR mhpmevent24, 0x111
WRITE_READ_CSR mhpmevent25, 0x111
WRITE_READ_CSR mhpmevent26, 0x111
WRITE_READ_CSR mhpmevent27, 0x111
WRITE_READ_CSR mhpmevent28, 0x111
WRITE_READ_CSR mhpmevent29, 0x111
WRITE_READ_CSR mhpmevent30, 0x111
WRITE_READ_CSR mhpmevent31, 0x111
END_TESTS

224
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S
View File

@ -31,142 +31,142 @@ s_file_begin:
GOTO_U_MODE 0x0, 0x0
# Attempt to write 0xbad to each of these CSRs and read the value back
# Attempt to write 0xAAA to each of these CSRs and read the value back
# should result in an illegal instruction for the write and read, respectively
# Supervisor Trap Setup
WRITE_READ_CSR sstatus, 0xbad
WRITE_READ_CSR sie, 0xbad
WRITE_READ_CSR stvec, 0xbad
WRITE_READ_CSR scounteren, 0xbad
WRITE_READ_CSR sstatus, 0xAAA
WRITE_READ_CSR sie, 0xAAA
WRITE_READ_CSR stvec, 0xAAA
WRITE_READ_CSR scounteren, 0xAAA
# Supervisor Configuration
# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
# WRITE_READ_CSR senvcfg, 0xAAA # *** these appear not to be implemented in the compile step of make???
# Supervisor Trap Handling
WRITE_READ_CSR sscratch, 0xbad
WRITE_READ_CSR sepc, 0xbad
WRITE_READ_CSR scause, 0xbad
WRITE_READ_CSR stval, 0xbad
WRITE_READ_CSR sip, 0xbad
WRITE_READ_CSR sscratch, 0xAAA
WRITE_READ_CSR sepc, 0xAAA
WRITE_READ_CSR scause, 0xAAA
WRITE_READ_CSR stval, 0xAAA
WRITE_READ_CSR sip, 0xAAA
# Supervisor Protection and Translation
WRITE_READ_CSR satp, 0xbad
WRITE_READ_CSR satp, 0xAAA
# Machine information Registers
WRITE_READ_CSR mvendorid, 0xbad
WRITE_READ_CSR marchid, 0xbad
WRITE_READ_CSR mimpid, 0xbad
WRITE_READ_CSR mhartid, 0xbad
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mvendorid, 0xAAA
WRITE_READ_CSR marchid, 0xAAA
WRITE_READ_CSR mimpid, 0xAAA
WRITE_READ_CSR mhartid, 0xAAA
# WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0xbad
WRITE_READ_CSR misa, 0xbad
WRITE_READ_CSR medeleg, 0xbad
WRITE_READ_CSR mideleg, 0xbad
WRITE_READ_CSR mie, 0xbad
WRITE_READ_CSR mtvec, 0xbad
WRITE_READ_CSR mcounteren, 0xbad
WRITE_READ_CSR mstatus, 0xAAA
WRITE_READ_CSR misa, 0xAAA
WRITE_READ_CSR medeleg, 0xAAA
WRITE_READ_CSR mideleg, 0xAAA
WRITE_READ_CSR mie, 0xAAA
WRITE_READ_CSR mtvec, 0xAAA
WRITE_READ_CSR mcounteren, 0xAAA
# Machine Trap Handling
WRITE_READ_CSR mscratch, 0xbad
WRITE_READ_CSR mepc, 0xbad
WRITE_READ_CSR mcause, 0xbad
WRITE_READ_CSR mtval, 0xbad
WRITE_READ_CSR mip, 0xbad
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0xbad
WRITE_READ_CSR mscratch, 0xAAA
WRITE_READ_CSR mepc, 0xAAA
WRITE_READ_CSR mcause, 0xAAA
WRITE_READ_CSR mtval, 0xAAA
WRITE_READ_CSR mip, 0xAAA
# WRITE_READ_CSR mtinst, 0xAAA # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0xAAA
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0xbad
# WRITE_READ_CSR menvcfg, 0xAAA # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0xAAA
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0xbad
WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpcfg0, 0xAAA
WRITE_READ_CSR pmpcfg2, 0xAAA # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpaddr0, 0xbad
WRITE_READ_CSR pmpaddr1, 0xbad
WRITE_READ_CSR pmpaddr2, 0xbad
WRITE_READ_CSR pmpaddr3, 0xbad
WRITE_READ_CSR pmpaddr4, 0xbad
WRITE_READ_CSR pmpaddr5, 0xbad
WRITE_READ_CSR pmpaddr6, 0xbad
WRITE_READ_CSR pmpaddr7, 0xbad
WRITE_READ_CSR pmpaddr8, 0xbad
WRITE_READ_CSR pmpaddr9, 0xbad
WRITE_READ_CSR pmpaddr10, 0xbad
WRITE_READ_CSR pmpaddr11, 0xbad
WRITE_READ_CSR pmpaddr12, 0xbad
WRITE_READ_CSR pmpaddr13, 0xbad
WRITE_READ_CSR pmpaddr14, 0xbad
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
WRITE_READ_CSR pmpaddr0, 0xAAA
WRITE_READ_CSR pmpaddr1, 0xAAA
WRITE_READ_CSR pmpaddr2, 0xAAA
WRITE_READ_CSR pmpaddr3, 0xAAA
WRITE_READ_CSR pmpaddr4, 0xAAA
WRITE_READ_CSR pmpaddr5, 0xAAA
WRITE_READ_CSR pmpaddr6, 0xAAA
WRITE_READ_CSR pmpaddr7, 0xAAA
WRITE_READ_CSR pmpaddr8, 0xAAA
WRITE_READ_CSR pmpaddr9, 0xAAA
WRITE_READ_CSR pmpaddr10, 0xAAA
WRITE_READ_CSR pmpaddr11, 0xAAA
WRITE_READ_CSR pmpaddr12, 0xAAA
WRITE_READ_CSR pmpaddr13, 0xAAA
WRITE_READ_CSR pmpaddr14, 0xAAA
WRITE_READ_CSR pmpaddr15, 0xAAA # only pmpcfg0...15 are enabled in our config
# Machine Counter/Timers
WRITE_READ_CSR mcycle, 0xbad
WRITE_READ_CSR minstret, 0xbad
WRITE_READ_CSR mhpmcounter3, 0xbad
WRITE_READ_CSR mhpmcounter4, 0xbad
WRITE_READ_CSR mhpmcounter5, 0xbad
WRITE_READ_CSR mhpmcounter6, 0xbad
WRITE_READ_CSR mhpmcounter7, 0xbad
WRITE_READ_CSR mhpmcounter8, 0xbad
WRITE_READ_CSR mhpmcounter9, 0xbad
WRITE_READ_CSR mhpmcounter10, 0xbad
WRITE_READ_CSR mhpmcounter11, 0xbad
WRITE_READ_CSR mhpmcounter12, 0xbad
WRITE_READ_CSR mhpmcounter13, 0xbad
WRITE_READ_CSR mhpmcounter14, 0xbad
WRITE_READ_CSR mhpmcounter15, 0xbad
WRITE_READ_CSR mhpmcounter16, 0xbad
WRITE_READ_CSR mhpmcounter17, 0xbad
WRITE_READ_CSR mhpmcounter18, 0xbad
WRITE_READ_CSR mhpmcounter19, 0xbad
WRITE_READ_CSR mhpmcounter20, 0xbad
WRITE_READ_CSR mhpmcounter21, 0xbad
WRITE_READ_CSR mhpmcounter22, 0xbad
WRITE_READ_CSR mhpmcounter23, 0xbad
WRITE_READ_CSR mhpmcounter24, 0xbad
WRITE_READ_CSR mhpmcounter25, 0xbad
WRITE_READ_CSR mhpmcounter26, 0xbad
WRITE_READ_CSR mhpmcounter27, 0xbad
WRITE_READ_CSR mhpmcounter28, 0xbad
WRITE_READ_CSR mhpmcounter29, 0xbad
WRITE_READ_CSR mhpmcounter30, 0xbad
WRITE_READ_CSR mhpmcounter31, 0xbad
WRITE_READ_CSR mcycle, 0xAAA
WRITE_READ_CSR minstret, 0xAAA
WRITE_READ_CSR mhpmcounter3, 0xAAA
WRITE_READ_CSR mhpmcounter4, 0xAAA
WRITE_READ_CSR mhpmcounter5, 0xAAA
WRITE_READ_CSR mhpmcounter6, 0xAAA
WRITE_READ_CSR mhpmcounter7, 0xAAA
WRITE_READ_CSR mhpmcounter8, 0xAAA
WRITE_READ_CSR mhpmcounter9, 0xAAA
WRITE_READ_CSR mhpmcounter10, 0xAAA
WRITE_READ_CSR mhpmcounter11, 0xAAA
WRITE_READ_CSR mhpmcounter12, 0xAAA
WRITE_READ_CSR mhpmcounter13, 0xAAA
WRITE_READ_CSR mhpmcounter14, 0xAAA
WRITE_READ_CSR mhpmcounter15, 0xAAA
WRITE_READ_CSR mhpmcounter16, 0xAAA
WRITE_READ_CSR mhpmcounter17, 0xAAA
WRITE_READ_CSR mhpmcounter18, 0xAAA
WRITE_READ_CSR mhpmcounter19, 0xAAA
WRITE_READ_CSR mhpmcounter20, 0xAAA
WRITE_READ_CSR mhpmcounter21, 0xAAA
WRITE_READ_CSR mhpmcounter22, 0xAAA
WRITE_READ_CSR mhpmcounter23, 0xAAA
WRITE_READ_CSR mhpmcounter24, 0xAAA
WRITE_READ_CSR mhpmcounter25, 0xAAA
WRITE_READ_CSR mhpmcounter26, 0xAAA
WRITE_READ_CSR mhpmcounter27, 0xAAA
WRITE_READ_CSR mhpmcounter28, 0xAAA
WRITE_READ_CSR mhpmcounter29, 0xAAA
WRITE_READ_CSR mhpmcounter30, 0xAAA
WRITE_READ_CSR mhpmcounter31, 0xAAA
# Machine Counter Setup
WRITE_READ_CSR mcountinhibit, 0xbad
WRITE_READ_CSR mhpmevent3, 0xbad
WRITE_READ_CSR mhpmevent4, 0xbad
WRITE_READ_CSR mhpmevent5, 0xbad
WRITE_READ_CSR mhpmevent6, 0xbad
WRITE_READ_CSR mhpmevent7, 0xbad
WRITE_READ_CSR mhpmevent8, 0xbad
WRITE_READ_CSR mhpmevent9, 0xbad
WRITE_READ_CSR mhpmevent10, 0xbad
WRITE_READ_CSR mhpmevent11, 0xbad
WRITE_READ_CSR mhpmevent12, 0xbad
WRITE_READ_CSR mhpmevent13, 0xbad
WRITE_READ_CSR mhpmevent14, 0xbad
WRITE_READ_CSR mhpmevent15, 0xbad
WRITE_READ_CSR mhpmevent16, 0xbad
WRITE_READ_CSR mhpmevent17, 0xbad
WRITE_READ_CSR mhpmevent18, 0xbad
WRITE_READ_CSR mhpmevent19, 0xbad
WRITE_READ_CSR mhpmevent20, 0xbad
WRITE_READ_CSR mhpmevent21, 0xbad
WRITE_READ_CSR mhpmevent22, 0xbad
WRITE_READ_CSR mhpmevent23, 0xbad
WRITE_READ_CSR mhpmevent24, 0xbad
WRITE_READ_CSR mhpmevent25, 0xbad
WRITE_READ_CSR mhpmevent26, 0xbad
WRITE_READ_CSR mhpmevent27, 0xbad
WRITE_READ_CSR mhpmevent28, 0xbad
WRITE_READ_CSR mhpmevent29, 0xbad
WRITE_READ_CSR mhpmevent30, 0xbad
WRITE_READ_CSR mhpmevent31, 0xbad
WRITE_READ_CSR mcountinhibit, 0xAAA
WRITE_READ_CSR mhpmevent3, 0xAAA
WRITE_READ_CSR mhpmevent4, 0xAAA
WRITE_READ_CSR mhpmevent5, 0xAAA
WRITE_READ_CSR mhpmevent6, 0xAAA
WRITE_READ_CSR mhpmevent7, 0xAAA
WRITE_READ_CSR mhpmevent8, 0xAAA
WRITE_READ_CSR mhpmevent9, 0xAAA
WRITE_READ_CSR mhpmevent10, 0xAAA
WRITE_READ_CSR mhpmevent11, 0xAAA
WRITE_READ_CSR mhpmevent12, 0xAAA
WRITE_READ_CSR mhpmevent13, 0xAAA
WRITE_READ_CSR mhpmevent14, 0xAAA
WRITE_READ_CSR mhpmevent15, 0xAAA
WRITE_READ_CSR mhpmevent16, 0xAAA
WRITE_READ_CSR mhpmevent17, 0xAAA
WRITE_READ_CSR mhpmevent18, 0xAAA
WRITE_READ_CSR mhpmevent19, 0xAAA
WRITE_READ_CSR mhpmevent20, 0xAAA
WRITE_READ_CSR mhpmevent21, 0xAAA
WRITE_READ_CSR mhpmevent22, 0xAAA
WRITE_READ_CSR mhpmevent23, 0xAAA
WRITE_READ_CSR mhpmevent24, 0xAAA
WRITE_READ_CSR mhpmevent25, 0xAAA
WRITE_READ_CSR mhpmevent26, 0xAAA
WRITE_READ_CSR mhpmevent27, 0xAAA
WRITE_READ_CSR mhpmevent28, 0xAAA
WRITE_READ_CSR mhpmevent29, 0xAAA
WRITE_READ_CSR mhpmevent30, 0xAAA
WRITE_READ_CSR mhpmevent31, 0xAAA
END_TESTS

44
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S Normal file
View File

@ -0,0 +1,44 @@
///////////////////////////////////////////
//
// WALLY-MMU
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-18
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
s_file_begin:
// Test 5.3.2.2: Machine ISA register test
// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs.
li x7, 0x111 // success value for read of nonzero misa
bnez x30, misa_nonzero
li x7, 0xbad // misa was zero, store bad value
misa_nonzero:
sw x7, 0(x6)
addi x6, x6, 4
addi x16, x16, 4
END_TESTS
TEST_STACK_AND_DATA

35
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S Normal file
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@ -0,0 +1,35 @@
///////////////////////////////////////////
//
// WALLY-scratch
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-20
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
s_file_begin:
// Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
END_TESTS
TEST_STACK_AND_DATA

39
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S Normal file
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@ -0,0 +1,39 @@
///////////////////////////////////////////
//
// WALLY-sscratch
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-20
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
s_file_begin:
// Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode
GOTO_S_MODE 0x0, 0x0
WRITE_READ_CSR sscratch, 0xAAA // check that sscratch is readable and writeable in supervisor mode
END_TESTS
TEST_STACK_AND_DATA

5
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
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@ -33,7 +33,10 @@ rv64i_sc_tests = \
WALLY-PMP \
WALLY-minfo-01 \
WALLY-CSR-permission-s-01 \
WALLY-CSR-permission-u-01
WALLY-CSR-permission-u-01 \
WALLY-misa-01 \
WALLY-scratch-01 \
WALLY-sscratch-s-01
target_tests_nosim = \
WALLY-PMA \

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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output Normal file
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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-scratch-01.reference_output Normal file
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tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sscratch-s-01.reference_output Normal file
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202
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S
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@ -34,123 +34,123 @@ s_file_begin:
GOTO_S_MODE 0x0, 0x0
# Attempt to write 0xbad to each of these CSRs and read the value back
# Attempt to write 0x111 to each of these CSRs and read the value back
# should result in an illegal instruction for the write and read, respectively
# Machine information Registers
WRITE_READ_CSR mvendorid, 0xbad
WRITE_READ_CSR marchid, 0xbad
WRITE_READ_CSR mimpid, 0xbad
WRITE_READ_CSR mhartid, 0xbad
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mvendorid, 0x111
WRITE_READ_CSR marchid, 0x111
WRITE_READ_CSR mimpid, 0x111
WRITE_READ_CSR mhartid, 0x111
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0xbad
WRITE_READ_CSR misa, 0xbad
WRITE_READ_CSR medeleg, 0xbad
WRITE_READ_CSR mideleg, 0xbad
WRITE_READ_CSR mie, 0xbad
WRITE_READ_CSR mtvec, 0xbad
WRITE_READ_CSR mcounteren, 0xbad
WRITE_READ_CSR mstatus, 0x111
WRITE_READ_CSR misa, 0x111
WRITE_READ_CSR medeleg, 0x111
WRITE_READ_CSR mideleg, 0x111
WRITE_READ_CSR mie, 0x111
WRITE_READ_CSR mtvec, 0x111
WRITE_READ_CSR mcounteren, 0x111
# Machine Trap Handling
WRITE_READ_CSR mscratch, 0xbad
WRITE_READ_CSR mepc, 0xbad
WRITE_READ_CSR mcause, 0xbad
WRITE_READ_CSR mtval, 0xbad
WRITE_READ_CSR mip, 0xbad
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0xbad
WRITE_READ_CSR mscratch, 0x111
WRITE_READ_CSR mepc, 0x111
WRITE_READ_CSR mcause, 0x111
WRITE_READ_CSR mtval, 0x111
WRITE_READ_CSR mip, 0x111
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0x111
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0xbad
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0x111
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0xbad
WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpcfg0, 0x111
WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpaddr0, 0xbad
WRITE_READ_CSR pmpaddr1, 0xbad
WRITE_READ_CSR pmpaddr2, 0xbad
WRITE_READ_CSR pmpaddr3, 0xbad
WRITE_READ_CSR pmpaddr4, 0xbad
WRITE_READ_CSR pmpaddr5, 0xbad
WRITE_READ_CSR pmpaddr6, 0xbad
WRITE_READ_CSR pmpaddr7, 0xbad
WRITE_READ_CSR pmpaddr8, 0xbad
WRITE_READ_CSR pmpaddr9, 0xbad
WRITE_READ_CSR pmpaddr10, 0xbad
WRITE_READ_CSR pmpaddr11, 0xbad
WRITE_READ_CSR pmpaddr12, 0xbad
WRITE_READ_CSR pmpaddr13, 0xbad
WRITE_READ_CSR pmpaddr14, 0xbad
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
WRITE_READ_CSR pmpaddr0, 0x111
WRITE_READ_CSR pmpaddr1, 0x111
WRITE_READ_CSR pmpaddr2, 0x111
WRITE_READ_CSR pmpaddr3, 0x111
WRITE_READ_CSR pmpaddr4, 0x111
WRITE_READ_CSR pmpaddr5, 0x111
WRITE_READ_CSR pmpaddr6, 0x111
WRITE_READ_CSR pmpaddr7, 0x111
WRITE_READ_CSR pmpaddr8, 0x111
WRITE_READ_CSR pmpaddr9, 0x111
WRITE_READ_CSR pmpaddr10, 0x111
WRITE_READ_CSR pmpaddr11, 0x111
WRITE_READ_CSR pmpaddr12, 0x111
WRITE_READ_CSR pmpaddr13, 0x111
WRITE_READ_CSR pmpaddr14, 0x111
WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
# Machine Counter/Timers
WRITE_READ_CSR mcycle, 0xbad
WRITE_READ_CSR minstret, 0xbad
WRITE_READ_CSR mhpmcounter3, 0xbad
WRITE_READ_CSR mhpmcounter4, 0xbad
WRITE_READ_CSR mhpmcounter5, 0xbad
WRITE_READ_CSR mhpmcounter6, 0xbad
WRITE_READ_CSR mhpmcounter7, 0xbad
WRITE_READ_CSR mhpmcounter8, 0xbad
WRITE_READ_CSR mhpmcounter9, 0xbad
WRITE_READ_CSR mhpmcounter10, 0xbad
WRITE_READ_CSR mhpmcounter11, 0xbad
WRITE_READ_CSR mhpmcounter12, 0xbad
WRITE_READ_CSR mhpmcounter13, 0xbad
WRITE_READ_CSR mhpmcounter14, 0xbad
WRITE_READ_CSR mhpmcounter15, 0xbad
WRITE_READ_CSR mhpmcounter16, 0xbad
WRITE_READ_CSR mhpmcounter17, 0xbad
WRITE_READ_CSR mhpmcounter18, 0xbad
WRITE_READ_CSR mhpmcounter19, 0xbad
WRITE_READ_CSR mhpmcounter20, 0xbad
WRITE_READ_CSR mhpmcounter21, 0xbad
WRITE_READ_CSR mhpmcounter22, 0xbad
WRITE_READ_CSR mhpmcounter23, 0xbad
WRITE_READ_CSR mhpmcounter24, 0xbad
WRITE_READ_CSR mhpmcounter25, 0xbad
WRITE_READ_CSR mhpmcounter26, 0xbad
WRITE_READ_CSR mhpmcounter27, 0xbad
WRITE_READ_CSR mhpmcounter28, 0xbad
WRITE_READ_CSR mhpmcounter29, 0xbad
WRITE_READ_CSR mhpmcounter30, 0xbad
WRITE_READ_CSR mhpmcounter31, 0xbad
WRITE_READ_CSR mcycle, 0x111
WRITE_READ_CSR minstret, 0x111
WRITE_READ_CSR mhpmcounter3, 0x111
WRITE_READ_CSR mhpmcounter4, 0x111
WRITE_READ_CSR mhpmcounter5, 0x111
WRITE_READ_CSR mhpmcounter6, 0x111
WRITE_READ_CSR mhpmcounter7, 0x111
WRITE_READ_CSR mhpmcounter8, 0x111
WRITE_READ_CSR mhpmcounter9, 0x111
WRITE_READ_CSR mhpmcounter10, 0x111
WRITE_READ_CSR mhpmcounter11, 0x111
WRITE_READ_CSR mhpmcounter12, 0x111
WRITE_READ_CSR mhpmcounter13, 0x111
WRITE_READ_CSR mhpmcounter14, 0x111
WRITE_READ_CSR mhpmcounter15, 0x111
WRITE_READ_CSR mhpmcounter16, 0x111
WRITE_READ_CSR mhpmcounter17, 0x111
WRITE_READ_CSR mhpmcounter18, 0x111
WRITE_READ_CSR mhpmcounter19, 0x111
WRITE_READ_CSR mhpmcounter20, 0x111
WRITE_READ_CSR mhpmcounter21, 0x111
WRITE_READ_CSR mhpmcounter22, 0x111
WRITE_READ_CSR mhpmcounter23, 0x111
WRITE_READ_CSR mhpmcounter24, 0x111
WRITE_READ_CSR mhpmcounter25, 0x111
WRITE_READ_CSR mhpmcounter26, 0x111
WRITE_READ_CSR mhpmcounter27, 0x111
WRITE_READ_CSR mhpmcounter28, 0x111
WRITE_READ_CSR mhpmcounter29, 0x111
WRITE_READ_CSR mhpmcounter30, 0x111
WRITE_READ_CSR mhpmcounter31, 0x111
# Machine Counter Setup
WRITE_READ_CSR mcountinhibit, 0xbad
WRITE_READ_CSR mhpmevent3, 0xbad
WRITE_READ_CSR mhpmevent4, 0xbad
WRITE_READ_CSR mhpmevent5, 0xbad
WRITE_READ_CSR mhpmevent6, 0xbad
WRITE_READ_CSR mhpmevent7, 0xbad
WRITE_READ_CSR mhpmevent8, 0xbad
WRITE_READ_CSR mhpmevent9, 0xbad
WRITE_READ_CSR mhpmevent10, 0xbad
WRITE_READ_CSR mhpmevent11, 0xbad
WRITE_READ_CSR mhpmevent12, 0xbad
WRITE_READ_CSR mhpmevent13, 0xbad
WRITE_READ_CSR mhpmevent14, 0xbad
WRITE_READ_CSR mhpmevent15, 0xbad
WRITE_READ_CSR mhpmevent16, 0xbad
WRITE_READ_CSR mhpmevent17, 0xbad
WRITE_READ_CSR mhpmevent18, 0xbad
WRITE_READ_CSR mhpmevent19, 0xbad
WRITE_READ_CSR mhpmevent20, 0xbad
WRITE_READ_CSR mhpmevent21, 0xbad
WRITE_READ_CSR mhpmevent22, 0xbad
WRITE_READ_CSR mhpmevent23, 0xbad
WRITE_READ_CSR mhpmevent24, 0xbad
WRITE_READ_CSR mhpmevent25, 0xbad
WRITE_READ_CSR mhpmevent26, 0xbad
WRITE_READ_CSR mhpmevent27, 0xbad
WRITE_READ_CSR mhpmevent28, 0xbad
WRITE_READ_CSR mhpmevent29, 0xbad
WRITE_READ_CSR mhpmevent30, 0xbad
WRITE_READ_CSR mhpmevent31, 0xbad
WRITE_READ_CSR mcountinhibit, 0x111
WRITE_READ_CSR mhpmevent3, 0x111
WRITE_READ_CSR mhpmevent4, 0x111
WRITE_READ_CSR mhpmevent5, 0x111
WRITE_READ_CSR mhpmevent6, 0x111
WRITE_READ_CSR mhpmevent7, 0x111
WRITE_READ_CSR mhpmevent8, 0x111
WRITE_READ_CSR mhpmevent9, 0x111
WRITE_READ_CSR mhpmevent10, 0x111
WRITE_READ_CSR mhpmevent11, 0x111
WRITE_READ_CSR mhpmevent12, 0x111
WRITE_READ_CSR mhpmevent13, 0x111
WRITE_READ_CSR mhpmevent14, 0x111
WRITE_READ_CSR mhpmevent15, 0x111
WRITE_READ_CSR mhpmevent16, 0x111
WRITE_READ_CSR mhpmevent17, 0x111
WRITE_READ_CSR mhpmevent18, 0x111
WRITE_READ_CSR mhpmevent19, 0x111
WRITE_READ_CSR mhpmevent20, 0x111
WRITE_READ_CSR mhpmevent21, 0x111
WRITE_READ_CSR mhpmevent22, 0x111
WRITE_READ_CSR mhpmevent23, 0x111
WRITE_READ_CSR mhpmevent24, 0x111
WRITE_READ_CSR mhpmevent25, 0x111
WRITE_READ_CSR mhpmevent26, 0x111
WRITE_READ_CSR mhpmevent27, 0x111
WRITE_READ_CSR mhpmevent28, 0x111
WRITE_READ_CSR mhpmevent29, 0x111
WRITE_READ_CSR mhpmevent30, 0x111
WRITE_READ_CSR mhpmevent31, 0x111
END_TESTS

224
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S
View File

@ -31,142 +31,142 @@ s_file_begin:
GOTO_U_MODE 0x0, 0x0
# Attempt to write 0xbad to each of these CSRs and read the value back
# Attempt to write 0x111 to each of these CSRs and read the value back
# should result in an illegal instruction for the write and read, respectively
# Supervisor Trap Setup
WRITE_READ_CSR sstatus, 0xbad
WRITE_READ_CSR sie, 0xbad
WRITE_READ_CSR stvec, 0xbad
WRITE_READ_CSR scounteren, 0xbad
WRITE_READ_CSR sstatus, 0x111
WRITE_READ_CSR sie, 0x111
WRITE_READ_CSR stvec, 0x111
WRITE_READ_CSR scounteren, 0x111
# Supervisor Configuration
# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR senvcfg, 0x111 # *** these appear not to be implemented in GCC
# Supervisor Trap Handling
WRITE_READ_CSR sscratch, 0xbad
WRITE_READ_CSR sepc, 0xbad
WRITE_READ_CSR scause, 0xbad
WRITE_READ_CSR stval, 0xbad
WRITE_READ_CSR sip, 0xbad
WRITE_READ_CSR sscratch, 0x111
WRITE_READ_CSR sepc, 0x111
WRITE_READ_CSR scause, 0x111
WRITE_READ_CSR stval, 0x111
WRITE_READ_CSR sip, 0x111
# Supervisor Protection and Translation
WRITE_READ_CSR satp, 0xbad
WRITE_READ_CSR satp, 0x111
# Machine information Registers
WRITE_READ_CSR mvendorid, 0xbad
WRITE_READ_CSR marchid, 0xbad
WRITE_READ_CSR mimpid, 0xbad
WRITE_READ_CSR mhartid, 0xbad
# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
WRITE_READ_CSR mvendorid, 0x111
WRITE_READ_CSR marchid, 0x111
WRITE_READ_CSR mimpid, 0x111
WRITE_READ_CSR mhartid, 0x111
# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
# Machine Trap Setup
WRITE_READ_CSR mstatus, 0xbad
WRITE_READ_CSR misa, 0xbad
WRITE_READ_CSR medeleg, 0xbad
WRITE_READ_CSR mideleg, 0xbad
WRITE_READ_CSR mie, 0xbad
WRITE_READ_CSR mtvec, 0xbad
WRITE_READ_CSR mcounteren, 0xbad
WRITE_READ_CSR mstatus, 0x111
WRITE_READ_CSR misa, 0x111
WRITE_READ_CSR medeleg, 0x111
WRITE_READ_CSR mideleg, 0x111
WRITE_READ_CSR mie, 0x111
WRITE_READ_CSR mtvec, 0x111
WRITE_READ_CSR mcounteren, 0x111
# Machine Trap Handling
WRITE_READ_CSR mscratch, 0xbad
WRITE_READ_CSR mepc, 0xbad
WRITE_READ_CSR mcause, 0xbad
WRITE_READ_CSR mtval, 0xbad
WRITE_READ_CSR mip, 0xbad
# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0xbad
WRITE_READ_CSR mscratch, 0x111
WRITE_READ_CSR mepc, 0x111
WRITE_READ_CSR mcause, 0x111
WRITE_READ_CSR mtval, 0x111
WRITE_READ_CSR mip, 0x111
# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mtval2, 0x111
# Machine Configuration
# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0xbad
# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
# WRITE_READ_CSR mseccgf, 0x111
# Machine Memory Protection
WRITE_READ_CSR pmpcfg0, 0xbad
WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpcfg0, 0x111
WRITE_READ_CSR pmpcfg2, 0x111 # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
WRITE_READ_CSR pmpaddr0, 0xbad
WRITE_READ_CSR pmpaddr1, 0xbad
WRITE_READ_CSR pmpaddr2, 0xbad
WRITE_READ_CSR pmpaddr3, 0xbad
WRITE_READ_CSR pmpaddr4, 0xbad
WRITE_READ_CSR pmpaddr5, 0xbad
WRITE_READ_CSR pmpaddr6, 0xbad
WRITE_READ_CSR pmpaddr7, 0xbad
WRITE_READ_CSR pmpaddr8, 0xbad
WRITE_READ_CSR pmpaddr9, 0xbad
WRITE_READ_CSR pmpaddr10, 0xbad
WRITE_READ_CSR pmpaddr11, 0xbad
WRITE_READ_CSR pmpaddr12, 0xbad
WRITE_READ_CSR pmpaddr13, 0xbad
WRITE_READ_CSR pmpaddr14, 0xbad
WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
WRITE_READ_CSR pmpaddr0, 0x111
WRITE_READ_CSR pmpaddr1, 0x111
WRITE_READ_CSR pmpaddr2, 0x111
WRITE_READ_CSR pmpaddr3, 0x111
WRITE_READ_CSR pmpaddr4, 0x111
WRITE_READ_CSR pmpaddr5, 0x111
WRITE_READ_CSR pmpaddr6, 0x111
WRITE_READ_CSR pmpaddr7, 0x111
WRITE_READ_CSR pmpaddr8, 0x111
WRITE_READ_CSR pmpaddr9, 0x111
WRITE_READ_CSR pmpaddr10, 0x111
WRITE_READ_CSR pmpaddr11, 0x111
WRITE_READ_CSR pmpaddr12, 0x111
WRITE_READ_CSR pmpaddr13, 0x111
WRITE_READ_CSR pmpaddr14, 0x111
WRITE_READ_CSR pmpaddr15, 0x111 # only pmpcfg0...15 are enabled in our config
# Machine Counter/Timers
WRITE_READ_CSR mcycle, 0xbad
WRITE_READ_CSR minstret, 0xbad
WRITE_READ_CSR mhpmcounter3, 0xbad
WRITE_READ_CSR mhpmcounter4, 0xbad
WRITE_READ_CSR mhpmcounter5, 0xbad
WRITE_READ_CSR mhpmcounter6, 0xbad
WRITE_READ_CSR mhpmcounter7, 0xbad
WRITE_READ_CSR mhpmcounter8, 0xbad
WRITE_READ_CSR mhpmcounter9, 0xbad
WRITE_READ_CSR mhpmcounter10, 0xbad
WRITE_READ_CSR mhpmcounter11, 0xbad
WRITE_READ_CSR mhpmcounter12, 0xbad
WRITE_READ_CSR mhpmcounter13, 0xbad
WRITE_READ_CSR mhpmcounter14, 0xbad
WRITE_READ_CSR mhpmcounter15, 0xbad
WRITE_READ_CSR mhpmcounter16, 0xbad
WRITE_READ_CSR mhpmcounter17, 0xbad
WRITE_READ_CSR mhpmcounter18, 0xbad
WRITE_READ_CSR mhpmcounter19, 0xbad
WRITE_READ_CSR mhpmcounter20, 0xbad
WRITE_READ_CSR mhpmcounter21, 0xbad
WRITE_READ_CSR mhpmcounter22, 0xbad
WRITE_READ_CSR mhpmcounter23, 0xbad
WRITE_READ_CSR mhpmcounter24, 0xbad
WRITE_READ_CSR mhpmcounter25, 0xbad
WRITE_READ_CSR mhpmcounter26, 0xbad
WRITE_READ_CSR mhpmcounter27, 0xbad
WRITE_READ_CSR mhpmcounter28, 0xbad
WRITE_READ_CSR mhpmcounter29, 0xbad
WRITE_READ_CSR mhpmcounter30, 0xbad
WRITE_READ_CSR mhpmcounter31, 0xbad
WRITE_READ_CSR mcycle, 0x111
WRITE_READ_CSR minstret, 0x111
WRITE_READ_CSR mhpmcounter3, 0x111
WRITE_READ_CSR mhpmcounter4, 0x111
WRITE_READ_CSR mhpmcounter5, 0x111
WRITE_READ_CSR mhpmcounter6, 0x111
WRITE_READ_CSR mhpmcounter7, 0x111
WRITE_READ_CSR mhpmcounter8, 0x111
WRITE_READ_CSR mhpmcounter9, 0x111
WRITE_READ_CSR mhpmcounter10, 0x111
WRITE_READ_CSR mhpmcounter11, 0x111
WRITE_READ_CSR mhpmcounter12, 0x111
WRITE_READ_CSR mhpmcounter13, 0x111
WRITE_READ_CSR mhpmcounter14, 0x111
WRITE_READ_CSR mhpmcounter15, 0x111
WRITE_READ_CSR mhpmcounter16, 0x111
WRITE_READ_CSR mhpmcounter17, 0x111
WRITE_READ_CSR mhpmcounter18, 0x111
WRITE_READ_CSR mhpmcounter19, 0x111
WRITE_READ_CSR mhpmcounter20, 0x111
WRITE_READ_CSR mhpmcounter21, 0x111
WRITE_READ_CSR mhpmcounter22, 0x111
WRITE_READ_CSR mhpmcounter23, 0x111
WRITE_READ_CSR mhpmcounter24, 0x111
WRITE_READ_CSR mhpmcounter25, 0x111
WRITE_READ_CSR mhpmcounter26, 0x111
WRITE_READ_CSR mhpmcounter27, 0x111
WRITE_READ_CSR mhpmcounter28, 0x111
WRITE_READ_CSR mhpmcounter29, 0x111
WRITE_READ_CSR mhpmcounter30, 0x111
WRITE_READ_CSR mhpmcounter31, 0x111
# Machine Counter Setup
WRITE_READ_CSR mcountinhibit, 0xbad
WRITE_READ_CSR mhpmevent3, 0xbad
WRITE_READ_CSR mhpmevent4, 0xbad
WRITE_READ_CSR mhpmevent5, 0xbad
WRITE_READ_CSR mhpmevent6, 0xbad
WRITE_READ_CSR mhpmevent7, 0xbad
WRITE_READ_CSR mhpmevent8, 0xbad
WRITE_READ_CSR mhpmevent9, 0xbad
WRITE_READ_CSR mhpmevent10, 0xbad
WRITE_READ_CSR mhpmevent11, 0xbad
WRITE_READ_CSR mhpmevent12, 0xbad
WRITE_READ_CSR mhpmevent13, 0xbad
WRITE_READ_CSR mhpmevent14, 0xbad
WRITE_READ_CSR mhpmevent15, 0xbad
WRITE_READ_CSR mhpmevent16, 0xbad
WRITE_READ_CSR mhpmevent17, 0xbad
WRITE_READ_CSR mhpmevent18, 0xbad
WRITE_READ_CSR mhpmevent19, 0xbad
WRITE_READ_CSR mhpmevent20, 0xbad
WRITE_READ_CSR mhpmevent21, 0xbad
WRITE_READ_CSR mhpmevent22, 0xbad
WRITE_READ_CSR mhpmevent23, 0xbad
WRITE_READ_CSR mhpmevent24, 0xbad
WRITE_READ_CSR mhpmevent25, 0xbad
WRITE_READ_CSR mhpmevent26, 0xbad
WRITE_READ_CSR mhpmevent27, 0xbad
WRITE_READ_CSR mhpmevent28, 0xbad
WRITE_READ_CSR mhpmevent29, 0xbad
WRITE_READ_CSR mhpmevent30, 0xbad
WRITE_READ_CSR mhpmevent31, 0xbad
WRITE_READ_CSR mcountinhibit, 0x111
WRITE_READ_CSR mhpmevent3, 0x111
WRITE_READ_CSR mhpmevent4, 0x111
WRITE_READ_CSR mhpmevent5, 0x111
WRITE_READ_CSR mhpmevent6, 0x111
WRITE_READ_CSR mhpmevent7, 0x111
WRITE_READ_CSR mhpmevent8, 0x111
WRITE_READ_CSR mhpmevent9, 0x111
WRITE_READ_CSR mhpmevent10, 0x111
WRITE_READ_CSR mhpmevent11, 0x111
WRITE_READ_CSR mhpmevent12, 0x111
WRITE_READ_CSR mhpmevent13, 0x111
WRITE_READ_CSR mhpmevent14, 0x111
WRITE_READ_CSR mhpmevent15, 0x111
WRITE_READ_CSR mhpmevent16, 0x111
WRITE_READ_CSR mhpmevent17, 0x111
WRITE_READ_CSR mhpmevent18, 0x111
WRITE_READ_CSR mhpmevent19, 0x111
WRITE_READ_CSR mhpmevent20, 0x111
WRITE_READ_CSR mhpmevent21, 0x111
WRITE_READ_CSR mhpmevent22, 0x111
WRITE_READ_CSR mhpmevent23, 0x111
WRITE_READ_CSR mhpmevent24, 0x111
WRITE_READ_CSR mhpmevent25, 0x111
WRITE_READ_CSR mhpmevent26, 0x111
WRITE_READ_CSR mhpmevent27, 0x111
WRITE_READ_CSR mhpmevent28, 0x111
WRITE_READ_CSR mhpmevent29, 0x111
WRITE_READ_CSR mhpmevent30, 0x111
WRITE_READ_CSR mhpmevent31, 0x111
END_TESTS

560
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@ -1,560 +0,0 @@
///////////////////////////////////////////
//
// WALLY-TEST-LIB-64.h
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-01-30
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
.macro INIT_TESTS
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
// ---------------------------------------------------------------------------------------------
// Initialization Overview:
//
// Initialize x6 as a virtual pointer to the test results
// Initialize x16 as a physical pointer to the test results
// Set up stack pointer (sp = x2)
// Set up the exception Handler, keeping the original handler in x4.
//
// ---------------------------------------------------------------------------------------------
// address for test results
la x6, test_1_res
la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers
// any time either is used, both must be updated.
// address for stack
la sp, top_of_stack
// trap handler setup
la x1, machine_trap_handler
csrrw x4, mtvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
li a0, 0
li a1, 0
li a2, 0 // reset trap handler inputs to zero
// go to first test!
j begin_test
// ---------------------------------------------------------------------------------------------
// General traps Handler
//
// Handles traps by branching to different behaviors based on mcause.
//
// Note that allowing the exception handler to change mode for a program is a huge security
// hole, but this is an expedient way of writing tests that need different modes
//
// input parameters:
//
// a0 (x10):
// 0: halt program with no failures
// 1: halt program with failure in x11 = a1
// 2: go to machine mode
// 3: go to supervisor mode
// 4: go to user mode
// others: do nothing
//
// a1 (x11):
// VPN for return address after changing privilege mode.
// This should be the base VPN with no offset.
// 0x0 : defaults to next instruction on the same page the trap was called on.
//
// a2 (x12):
// Pagetype of the current address VPN before changing privilge mode
// Used so that we can know how many bits of the adress are the offset.
// Ignored if a1 == 0x0
// 0: Kilopage
// 1: Megapage
// 2: Gigapage
// 3: Terapage
//
// --------------------------------------------------------------------------------------------
machine_trap_handler:
// The processor is always in machine mode when a trap takes us here
// save registers on stack before using
sd x1, -8(sp)
sd x5, -16(sp)
// Record trap
csrr x1, mcause // record the mcause
sd x1, 0(x16)
addi x6, x6, 8
addi x16, x16, 8 // update pointers for logging results
// Respond to trap based on cause
// All interrupts should return after being logged
li x5, 0x8000000000000000 // if msb is set, it is an interrupt
and x5, x5, x1
bnez x5, trapreturn // return from interrupt
// Other trap handling is specified in the vector Table
slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
la x5, trap_handler_vector_table
add x5, x5, x1 // compute address of vector in Table
ld x5, 0(x5) // fectch address of handler from vector Table
jr x5 // and jump to the handler
segfault:
ld x5, -16(sp) // restore registers from stack before faulting
ld x1, -8(sp)
j terminate_test // halt program.
trapreturn:
// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
csrr x1, mepc // get the mepc
addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction,
// ******** but in the handler, we work in M mode with physical addresses
// This means the address in mepc is suddenly pointing somewhere else.
// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible)
// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed.
// lw x5, 0(x1) // read the faulting instruction
// li x1, 3 // check bottom 2 bits of instruction to see if compressed
// and x5, x5, x1 // mask the other bits
// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed
// trapreturn_compressed:
// csrr x1, mepc // get the mepc again
// addi x1, x1, 2 // add 2 to find the next instruction
// j trapreturn_specified // and return
// trapreturn_uncompressed:
// csrr x1, mepc // get the mepc again
// addi x1, x1, 4 // add 4 to find the next instruction
trapreturn_specified:
// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
// so that when we return to a new virtual address, they're all in the right spot as well.
beqz a1, trapreturn_finished // either update values, of go to default return address.
la x5, trap_return_pagetype_table
slli a2, a2, 3
add x5, x5, a2
ld a2, 0(x5) // a2 = number of offset bits in current page type
li x5, 1
sll x5, x5, a2
addi x5, x5, -1 // x5 = mask bits for offset into current pagetype
// reset the top of the stack, x1
ld x7, -8(sp)
and x7, x5, x7 // x7 = offset for x1
add x7, x7, a1 // x7 = new address for x1
sd x7, -8(sp)
// reset the second spot in the stack, x5
ld x7, -16(sp)
and x7, x5, x7 // x7 = offset for x5
add x7, x7, a1 // x7 = new address for x5
sd x7, -16(sp)
// reset x6, the pointer for the virtual address of the output of the tests
and x7, x5, x6 // x7 = offset for x6
add x6, x7, a1 // x6 = new address for the result pointer
// set return address, stored temporarily in x1, to the next instruction, but in the new virtual page.
and x1, x5, x1 // x1 = offset for the return address
add x1, x1, a1 // x1 = new return address.
li a1, 0
li a2, 0 // reset trapreturn inputs to the trap handler
trapreturn_finished:
csrw mepc, x1 // update the mepc with address of next instruction
ld x5, -16(sp) // restore registers from stack before returning
ld x1, -8(sp)
mret // return from trap
ecallhandler:
// Check input parameter a0. encoding above.
// *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
li x5, 2 // case 2: change to machine mode
beq a0, x5, ecallhandler_changetomachinemode
li x5, 3 // case 3: change to supervisor mode
beq a0, x5, ecallhandler_changetosupervisormode
li x5, 4 // case 4: change to user mode
beq a0, x5, ecallhandler_changetousermode
// unsupported ecalls should segfault
j segfault
ecallhandler_changetomachinemode:
// Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
li x1, 0b1100000000000
csrs mstatus, x1
j trapreturn
ecallhandler_changetosupervisormode:
// Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
li x1, 0b1100000000000
csrc mstatus, x1
li x1, 0b0100000000000
csrs mstatus, x1
j trapreturn
ecallhandler_changetousermode:
// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
li x1, 0b1100000000000
csrc mstatus, x1
j trapreturn
instrfault:
ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page)
j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
illegalinstr:
j trapreturn // return to the code after recording the mcause
accessfault:
// *** What do I have to do here?
j trapreturn
// Table of trap behavior
// lists what to do on each exception (not interrupts)
// unexpected exceptions should cause segfaults for easy detection
// Expected exceptions should increment the EPC to the next instruction and return
.align 3 // aligns this data table to an 8 byte boundary
trap_handler_vector_table:
.8byte segfault // 0: instruction address misaligned
.8byte instrfault // 1: instruction access fault
.8byte illegalinstr // 2: illegal instruction
.8byte segfault // 3: breakpoint
.8byte segfault // 4: load address misaligned
.8byte accessfault // 5: load access fault
.8byte segfault // 6: store address misaligned
.8byte accessfault // 7: store access fault
.8byte ecallhandler // 8: ecall from U-mode
.8byte ecallhandler // 9: ecall from S-mode
.8byte segfault // 10: reserved
.8byte ecallhandler // 11: ecall from M-mode
.8byte instrfault // 12: instruction page fault
.8byte trapreturn // 13: load page fault
.8byte segfault // 14: reserved
.8byte trapreturn // 15: store page fault
.align 3
trap_return_pagetype_table:
.8byte 0xC // 0: kilopage has 12 offset bits
.8byte 0x15 // 1: megapage has 21 offset bits
.8byte 0x1E // 2: gigapage has 30 offset bits
.8byte 0x27 // 3: terapage has 39 offset bits
begin_test: // label here to jump to so we dont go through the trap handler before starting the test
.endm // Ends the initialization macro that set up the begginnning of the tests and the trap handler.
// Test Summary table!
// Test Name : Description : Fault output value : Normal output values
// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------
// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None
// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None
// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None
// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None
// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111)
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
// goto_baremetal : satp.MODE = bare metal : None : None
// goto_sv39 : satp.MODE = sv39 : None : None
// goto_sv48 : satp.MODE = sv48 : None : None
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR
// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11
// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value
.macro write64_test ADDR VAL
// attempt to write VAL to ADDR
// Success outputs:
// None
// Fault outputs:
// 0x6: misaligned address
// 0x7: access fault
// 0xf: page fault
li x29, \VAL
li x30, \ADDR
sd x29, 0(x30)
.endm
.macro write32_test ADDR VAL
// all write tests have the same description/outputs as write64
li x29, \VAL
li x30, \ADDR
sw x29, 0(x30)
.endm
.macro write16_test ADDR VAL
// all write tests have the same description/outputs as write64
li x29, \VAL
li x30, \ADDR
sh x29, 0(x30)
.endm
.macro write08_test ADDR VAL
// all write tests have the same description/outputs as write64
li x29, \VAL
li x30, \ADDR
sb x29, 0(x30)
.endm
.macro read64_test ADDR
// Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value
// Success outputs:
// value read out from ADDR
// Fault outputs:
// One of the following followed by 0xBAD
// 0x4: misaligned address
// 0x5: access fault
// 0xD: page fault
li x7, 0xBAD // bad value that will be overwritten on good reads.
li x29, \ADDR
ld x7, 0(x29)
sd x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
.endm
.macro read32_test ADDR
// All reads have the same description/outputs as read64.
// They will store the sign extended value of what was read out at ADDR
li x7, 0xBAD // bad value that will be overwritten on good reads.
li x29, \ADDR
lw x7, 0(x29)
sd x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
.endm
.macro read16_test ADDR
// All reads have the same description/outputs as read64.
// They will store the sign extended value of what was read out at ADDR
li x7, 0xBAD // bad value that will be overwritten on good reads.
li x29, \ADDR
lh x7, 0(x29)
sd x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
.endm
.macro read08_test ADDR
// All reads have the same description/outputs as read64.
// They will store the sign extended value of what was read out at ADDR
li x7, 0xBAD // bad value that will be overwritten on good reads.
li x29, \ADDR
lb x7, 0(x29)
sd x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
.endm
// These goto_x_mode tests all involve invoking the trap handler,
// So their outputs are inevitably:
// 0x8: test called from U mode
// 0x9: test called from S mode
// 0xB: test called from M mode
// they generally do not fault or cause issues as long as these modes are enabled
// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
.macro goto_m_mode RETURN_VPN RETURN_PAGETYPE
li a0, 2 // determine trap handler behavior (go to supervisor mode)
li a1, \RETURN_VPN // return VPN
li a2, \RETURN_PAGETYPE // return page types
ecall // writes mcause to the output.
// now in S mode
.endm
.macro goto_s_mode RETURN_VPN RETURN_PAGETYPE
li a0, 3 // determine trap handler behavior (go to supervisor mode)
li a1, \RETURN_VPN // return VPN
li a2, \RETURN_PAGETYPE // return page types
ecall // writes mcause to the output.
// now in S mode
.endm
.macro goto_u_mode RETURN_VPN RETURN_PAGETYPE
li a0, 4 // determine trap handler behavior (go to supervisor mode)
li a1, \RETURN_VPN // return VPN
li a2, \RETURN_PAGETYPE // return page types
ecall // writes mcause to the output.
// now in S mode
.endm
// These tests change virtual memory settings, turning it on/off and changing between types.
// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy?
.macro goto_baremetal
// Turn translation off
li x7, 0 // satp.MODE value for bare metal (0)
slli x7, x7, 60
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
add x7, x7, x28
csrw satp, x7
sfence.vma x0, x0 // *** flushes global pte's as well
.endm
.macro goto_sv39
// Turn on sv39 virtual memory
li x7, 8 // satp.MODE value for Sv39 (8)
slli x7, x7, 60
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
add x7, x7, x28
csrw satp, x7
sfence.vma x0, x0 // *** flushes global pte's as well
.endm
.macro goto_sv48
// Turn on sv48 virtual memory
li x7, 9 // satp.MODE value for Sv39 (8)
slli x7, x7, 60
li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location
add x7, x7, x28
csrw satp, x7
sfence.vma x0, x0 // *** flushes global pte's as well
.endm
.macro write_read_csr CSR VAL
// attempt to write CSR with VAL. Note: this also tests read access to CSR
// Success outputs:
// value read back out from CSR after writing
// Fault outputs:
// The previous CSR value before write attempt
// *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
li x30, 0xbad // load bad value to be overwritten by csrr
li x29, \VAL
csrw \CSR\(), x29
csrr x30, \CSR
sd x30, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
.endm
.macro csr_r_access CSR
// verify that a csr is accessible to read but not to write
// Success outputs:
// 0x2, then
// 0x11 *** consider changing to something more meaningful
// Fault outputs:
// 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault?
csrr x29, \CSR
csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
csrr x30, \CSR
bne x30, x29, 1f // 1f represents write_access
li x30, 0x11 // Write failed, confirming read only permissions.
j 2f // j r_access_end
1: // w_access (write succeeded, violating read-only)
li x30, 0xBAD
2: // r_access end
sd x30, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
.endm
.macro execute_at_address ADDR
// Execute the code already written to ADDR, returning the value in x7.
// *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
// Assumes the code modifies x7, usually to become 0x111.
// Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret)
// Success outputs:
// modified value of x7. (0x111 if you use the sample code)
// Fault outputs:
// One of the following followed by 0xBAD
// 0x0: misaligned address
// 0x1: access fault
// 0xC: page fault
fence.i // forces caches and main memory to sync so execution code written to ADDR can run.
li x7, 0xBAD
li x28, \ADDR
jalr x28 // jump to executable test code
sd x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
.endm
.macro END_TESTS
// invokes one final ecall to return to machine mode then terminates this program, so the output is
// 0x8: termination called from U mode
// 0x9: termination called from S mode
// 0xB: termination called from M mode
terminate_test:
li a0, 2 // Trap handler behavior (go to machine mode)
ecall // writes mcause to the output.
csrw mtvec, x4 // restore original trap handler to halt program
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
.align 3 // align stack to 8 byte boundary
bottom_of_stack:
.fill 1024, 4, 0xdeadbeef
top_of_stack:
RVMODEL_DATA_BEGIN
test_1_res:
.fill 1024, 4, 0xdeadbeef
RVMODEL_DATA_END
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
.endm // ends the macro that terminates this test program.

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///////////////////////////////////////////
//
// WALLY-MMU
// WALLY-minfo
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//

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///////////////////////////////////////////
//
// WALLY-misa
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-18
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
s_file_begin:
// Test 5.3.2.2: Machine ISA register test
// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs.
li x7, 0x111 // success value for read of nonzero misa
bnez x30, misa_nonzero
li x7, 0xbad // misa was zero, store bad value
misa_nonzero:
sd x7, 0(x6)
addi x6, x6, 8
addi x16, x16, 8
END_TESTS
TEST_STACK_AND_DATA

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///////////////////////////////////////////
//
// WALLY-scratch
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-20
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
s_file_begin:
// Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
END_TESTS
TEST_STACK_AND_DATA

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///////////////////////////////////////////
//
// WALLY-sscratch
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-02-20
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
INIT_TESTS
s_file_begin:
// Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode
GOTO_S_MODE 0x0, 0x0
WRITE_READ_CSR sscratch, 0xAAA // check that sscratch is readable and writeable in supervisor mode
END_TESTS
TEST_STACK_AND_DATA