ushakya22 3abc2c0592 - created new testbench file instead of having it at the bottom of the srt file ... - uses unpacker to parse 64 bit floating point numbers - updated testbench to read from new testvectors generated by exptestbench Notes: MEM_WIDTH updated to be 64*3 Input numbers and output result is 64 bit number MEM_SIZE set to 60000		2022-02-21 16:24:50 +00:00
..
config	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
fpu-testfloat/FMA/tbgen	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Accidentally cleared dirty bit when setting access bit in hptw.	2022-02-17 16:20:20 -06:00
src	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-18 23:08:47 +00:00
srt	- created new testbench file instead of having it at the bottom of the srt file	2022-02-21 16:24:50 +00:00
testbench	added scratch register tests for 64 and 32 bits	2022-02-21 07:03:12 +00:00