108 Commits

Author	SHA1	Message	Date
David Harris	0abfe5cb55	Fixed some lint errors in derived configs	2024-01-31 11:39:59 -08:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
David Harris	e8dde265be	More coverage: CacheWay	2024-01-26 16:14:36 -08:00
David Harris	3620a10c0b	Improved hptw and I CacheWays coverage	2024-01-26 14:55:51 -08:00
David Harris	4ffa5e7b0a	Coverage improvements	2024-01-22 09:49:24 -08:00
Rose Thompson	2d3dc55986	Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting.	2024-01-17 12:19:10 -06:00
Rose Thompson	730efefc41	Cleanup.	2023-12-29 16:18:30 -06:00
Rose Thompson	6a787981c2	Restored cache store delay hazard.	2023-12-29 16:10:27 -06:00
David Harris	e8df856fdb	Renamed CMOp to CMOpM in mmu and cache	2023-12-25 05:57:41 -08:00
Rose Thompson	5062a8c89c	Added parameter for cache's SRAM length. ... Progress towards verilator support.	2023-12-18 12:50:49 -06:00
Rose Thompson	1d36ce3328	Fixed lint issue.	2023-12-18 12:03:54 -06:00
Rose Thompson	1ca9a8be6d	I think I solved the AMO/store hazard issue introduced by removing the store delay hazard.	2023-12-14 16:31:02 -06:00
Rose Thompson	e089b421bb	Got it working for the cache.	2023-12-13 20:24:46 -06:00
Rose Thompson	f592baa741	Closer.	2023-12-13 18:15:32 -06:00
Rose Thompson	eeced05f33	More progress towards store delay reduction.	2023-12-13 15:56:29 -06:00
Rose Thompson	f3d43a7713	Progress on reducing store stall in d cache.	2023-12-13 15:34:21 -06:00
Rose Thompson	13bb5d845b	On the way to solving the store delay hazard.	2023-12-13 10:39:01 -06:00
Rose Thompson	9348025727	Cachefsm simplifications.	2023-12-03 18:19:00 -06:00
Rose Thompson	3bef2a2361	Better name for cache signals.	2023-12-03 15:49:06 -06:00
Rose Thompson	025b04ae8b	Minior cleanup.	2023-11-29 19:44:59 -06:00
Rose Thompson	ab68a76e77	LineDirty is either the Victim Way or the Flush way dirty, but never the hitway dirty. CBO instructions require hitway dirty. However we cannot mux hitway dirty into LineDirty wihtout creating a combinational loop so we need a separate port.	2023-11-29 17:58:39 -06:00
Rose Thompson	80336493f5	Cleaned up redundant ZICBOM/Z_SUPPORTED.	2023-11-29 15:20:49 -06:00
Rose Thompson	0229df4a0f	Oups. Introduced undetected bug into the cache's cbo insructions.	2023-11-28 01:03:48 -06:00
Rose Thompson	337903d8dd	More cache simplifications.	2023-11-27 14:59:42 -06:00
Rose Thompson	08549446ef	Reduced cache fsm complexity.	2023-11-27 13:13:36 -06:00
Rose Thompson	c3da4c3c31	Clarified names in cacheway.	2023-11-27 12:56:11 -06:00
Rose Thompson	d7ef490c12	Sutble bug in the cacheway logic for cacheline invalidation.	2023-11-27 01:27:09 -06:00
Rose Thompson	58d89cc347	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-11-21 10:48:05 -06:00
David Harris	f89fd8a7fe	removed unused cache signals	2023-11-20 23:16:35 -08:00
Rose Thompson	1acc3951c8	More simplifications.	2023-11-21 00:19:24 -06:00
Rose Thompson	1d811b085c	More cleanup.	2023-11-21 00:14:59 -06:00
Rose Thompson	d2a747bf3d	cleanup.	2023-11-20 23:59:40 -06:00
Rose Thompson	70eb110a9c	More optimizations to simplify cmo logic.	2023-11-20 22:13:31 -06:00
Rose Thompson	52ac07ce8d	Removed the CMO_WRITEBACK state from the cache and unused signals.	2023-11-20 20:56:30 -06:00
Rose Thompson	667fe035c0	Simplified CMO.Zero fsm implementation slightly.	2023-11-20 17:01:43 -06:00
Rose Thompson	23e05cb8b2	Finally have the cbo way muxing controls reduced to something sane.	2023-11-20 11:28:03 -06:00
Rose Thompson	b74bfbeefd	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
David Harris	1f2899de14	Modified rams to take USE_SRAM rather than P to facilitate synthesis	2023-11-03 05:44:13 -07:00
Rose Thompson	dce3c85105	Progress.	2023-10-27 16:31:22 -05:00
David Harris	6e7c0547a1	Modified log2 coding to avoid synthesis warning	2023-10-19 11:16:02 -07:00
Ross Thompson	11a3fd9314	Slight modification to cachefsm.	2023-09-05 14:07:58 -05:00
Ross Thompson	85ba53eeaf	Merge pull request #406 from magpyed/cachesim_fix ... Properly gate LRUWriteEn with ~FlushStage	2023-09-05 11:10:58 -05:00
Limnanthes Serafini	6c78942685	Properly gate LRUWriteEn with ~FlushStage	2023-09-01 23:31:02 -07:00
David Harris	e75ceb044f	Improved tlb and controller coverage; fixed exclusions on broken lines	2023-08-31 00:27:47 -07:00
Ross Thompson	99455ad851	Fixed minor performance bug with CBOZ.	2023-08-24 17:08:20 -05:00
Ross Thompson	914b6f9734	Now have CBOZ instructions working!	2023-08-24 16:47:35 -05:00
Ross Thompson	c2a9fbb1fc	Fixed bug with the cbo.inval clearing already cleared lines.	2023-08-21 17:51:51 -05:00
Ross Thompson	05d590b0b9	Fixed issue when with flush miss.	2023-08-18 16:36:13 -05:00
Ross Thompson	fc3fccafe9	Now we have invalidate, clean, and flush working.	2023-08-18 16:32:22 -05:00
Ross Thompson	5c408454b8	Might have working cbo clean and flush instructions.	2023-08-18 14:48:21 -05:00