Ross Thompson 7497422667 Changed several things. ... Removed the need to use async flip flops in SDC. Added arrs, a synchronizer for reset. I think this works with the real FPGA hardware. The last build did not include this arrs but it worked.		2021-11-12 11:13:50 -06:00
..
common	Merge branch 'main' into fpga	2021-10-11 18:17:58 -05:00
fp	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
imperas-boottim.txt
testbench-coremark_bare.sv
testbench-coremark.sv
testbench-f64.sv	Clean up some signals - beautification onging	2021-10-14 17:12:00 -05:00
testbench-fpga.sv	Changed several things.	2021-11-12 11:13:50 -06:00
testbench-linux.sv	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
testbench-privileged.sv
testbench.sv	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
tests.vh	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00