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CVW_v0.8

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• a5f773220e Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes. Ross Thompson 2022-01-18 17:19:33 -0600
• ebf9f5d526 riscvsingle reparittioned to match Ch4 David Harris 2022-01-17 16:57:32 +0000
• 55b4423329 Added E extension, and downloaded riscv-dv and embench-iot to addins David Harris 2022-01-17 14:42:59 +0000
• b63e53bbdb Defined rv32e and rv32emc configs David Harris 2022-01-17 14:01:01 +0000
• bd320c2f76 lsu cleanup down to 346 lines David Harris 2022-01-15 01:19:44 +0000
• 325724f556 LSU Cleanup David Harris 2022-01-15 01:11:17 +0000
• 6febce0001 Moved Dcache into bus block David Harris 2022-01-15 00:39:07 +0000
• fd13272d4c Renamed LSUStall to LSUStallM David Harris 2022-01-15 00:24:16 +0000
• db2271b7e0 LSU cleanup David Harris 2022-01-15 00:11:30 +0000
• dab3c754d7 LSU cleanup David Harris 2022-01-15 00:03:03 +0000
• 2bf4676ff8 LSU cleanup David Harris 2022-01-14 23:55:27 +0000
• 03010845f5 Fixed spillthreshold warning. Ross Thompson 2022-01-14 17:23:39 -0600
• ba10e9dfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-14 17:16:53 -0600
• 43abf25417 moved fp to tests David Harris 2022-01-14 23:05:59 +0000
• 218a8e6eaa LSU partitioning David Harris 2022-01-14 23:02:28 +0000
• ae6792e354 Moved fp tests from testbench to tests/fp David Harris 2022-01-14 23:00:46 +0000
• 73ad5715f4 Cleanup IFU comments. Ross Thompson 2022-01-14 15:06:30 -0600
• b8f4eb2997 Optimization in the ifu. Please note this optimization is not strictly correct, but is possible. See comments in the ifu source code for details. Ross Thompson 2022-01-14 12:16:48 -0600
• 2e8f5e06bd More ifu cleanup. Ross Thompson 2022-01-14 11:19:12 -0600
• 3bec276862 Added tim only test to regression-wally. Minor cleanup to ifu. Ross Thompson 2022-01-14 11:13:06 -0600
• e0e30c1e9e Update to TestFloat for scripts so can run automatically once TestFloat/Softfloat is compiled. Slight change to the README as well. James E. Stine 2022-01-14 09:25:37 -0600
• a973681a90 Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. Ross Thompson 2022-01-13 22:21:43 -0600
• aad28366d7 Partial local dtim in lsu configuration. Ross Thompson 2022-01-13 17:00:46 -0600
• 602867f54e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-13 21:46:00 +0000
• 7d13740a11 Mixed C and assembly language test cases; SRT initial version passing tests David Harris 2022-01-13 21:45:54 +0000
• e6e3b0607a Merge branch 'testDivInterruptInterlock' into main Ross Thompson 2022-01-13 11:21:48 -0600
• f870b8b3d3 Fixed interger divide so it can be interrupted. Ross Thompson 2022-01-13 11:16:50 -0600
• 66f3259984 Removed unused inputs to hptw. Ross Thompson 2022-01-13 11:04:48 -0600
• a23e6efd5c Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu. Ross Thompson 2022-01-12 17:41:39 -0600
• 85b5dc08a8 Fixed support to allow spills and no icache. Ross Thompson 2022-01-12 17:25:16 -0600
• e06fb923a1 Better solution to the integer divider interrupt interaction. Ross Thompson 2022-01-12 14:22:18 -0600
• e5262b80a6 Merge branch 'testDivInterruptInterlock' of github.com:davidharrishmc/riscv-wally into testDivInterruptInterlock Ross Thompson 2022-01-12 14:17:49 -0600
• 11f1613d59 Added additional fsm to ILA. Ross Thompson 2022-01-09 17:10:57 -0600
• d8173745bb Possible fix for the TrapM DTLBMiss suppression. Ross Thompson 2022-01-09 14:22:14 -0600
• cd75bf98e1 If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM. Ross Thompson 2022-01-08 20:49:45 -0600
• b294f1fbb0 Oups. My hack for DivE interrupt prevention was wrong. Ross Thompson 2022-01-08 17:21:27 -0600
• 459f4bd3b4 Hack "fix" to prevent interrupt from occuring during an integer divide. This is not the desired solution but will allow continued debuging of linux. Ross Thompson 2022-01-08 14:21:58 -0600
• 960af4b70f Set rv32ic to not use icache. Ross Thompson 2022-01-12 14:10:09 -0600
• f18684efbf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-12 13:29:19 -0600
• 786a772444 Improve wavefile by adding performance counters. Ross Thompson 2022-01-12 10:53:29 -0600
• 4b7ee9815e C sum example David Harris 2022-01-12 09:04:41 +0000
• f91b635652 remove extraneous James E. Stine 2022-01-11 16:01:48 -0600
• 14e53099f8 Update on assembly simple/spike James E. Stine 2022-01-11 15:59:56 -0600
• 10921accdb Added inline assembly to simple David Harris 2022-01-11 21:32:30 +0000
• 02f6030c02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-11 21:01:50 +0000
• 486cfdc3a5 Added C test cases David Harris 2022-01-11 21:01:48 +0000
• c251144460 Fixed PMA regions, Added passing PMA tests to regression Kip Macsai-Goren 2022-01-10 22:08:26 +0000
• 0b3d3b768b Do file for riscvsingle David Harris 2022-01-10 16:26:18 +0000
• 86857a877b Added fulladder example files David Harris 2022-01-10 16:15:05 +0000
• 3a2b459439 Merged coremark changes David Harris 2022-01-10 05:09:28 +0000
• 401a5b1779 Removed unused coremark_bare David Harris 2022-01-10 05:05:55 +0000
• 39d5570d2c Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark. David Harris 2022-01-10 05:04:13 +0000
• 73c488914f Added icache access and icache miss to performance counters. Ross Thompson 2022-01-09 22:56:56 -0600
• 04ea93aa27 Added performance counters to wavefile. Ross Thompson 2022-01-09 22:42:14 -0600
• ae927e2bc6 Fixed wavefile. Converted coremark to use elf2hex. Ross Thompson 2022-01-09 22:03:10 -0600
• 3447c23d9b Added additional fsm to ILA. Ross Thompson 2022-01-09 17:10:57 -0600
• fbff9edc8f Possible fix for the TrapM DTLBMiss suppression. Ross Thompson 2022-01-09 14:22:14 -0600
• 54aab6cdde comment cleanup Kip Macsai-Goren 2022-01-09 18:16:42 +0000
• 53ea1360ce updated PMA tests, everything passes except successful writes to protected regions. Kip Macsai-Goren 2022-01-09 18:16:00 +0000
• 5f7323f25f changed test case types to lookup table instead of beq's Kip Macsai-Goren 2022-01-09 16:56:16 +0000
• 0212260eef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-09 14:39:33 +0000
• c1d2199dc6 Fixed RISCV path in coremark Makefile David Harris 2022-01-09 14:39:22 +0000
• 8fb5500be8 If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss. This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM. Ross Thompson 2022-01-08 20:49:45 -0600
• c7c8b128b3 Oups. My hack for DivE interrupt prevention was wrong. Ross Thompson 2022-01-08 17:21:27 -0600
• aa59dfa095 Hack "fix" to prevent interrupt from occuring during an integer divide. This is not the desired solution but will allow continued debuging of linux. Ross Thompson 2022-01-08 14:21:58 -0600
• d14dffd010 Updated debug constraints again to match changes in verilog. Ross Thompson 2022-01-08 13:28:51 -0600
• 0f14d2ec88 Added advanced Vivado debug scripts. Ross Thompson 2022-01-07 17:56:40 -0600
• 509a0cd3f8 Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu only at the start of a request. Pending interrupt was used to start one of these suppressions; however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an interrupt becam pending then the the next request (eviction) made by the cache was also suppressed. This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request to the bus fsm, but the pending interrupt ignored the request. Ross Thompson 2022-01-07 17:55:34 -0600
• 54d852f6ae renamed regression-wally.py to regression-wally David Harris 2022-01-07 17:47:38 +0000
• bea6d0856d Testbench directory cleanup David Harris 2022-01-07 17:02:16 +0000
• 120fb7863f Reformatted MIT license to 95 characters David Harris 2022-01-07 12:58:40 +0000
• fedb9d3287 moved proposed-sdc David Harris 2022-01-07 12:44:21 +0000
• 40af3abef9 piplined directory cleanup David Harris 2022-01-07 12:43:50 +0000
• c97572d209 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-07 05:39:16 +0000
• c8d47fc7c3 Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata. Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-06 23:28:02 -0600
• 2a64b1bc95 Used .* in wrapper David Harris 2022-01-07 05:23:42 +0000
• 0fddceffa6 Modified the mmu to not mux the lower 12 bits of the physical address and instead directly assign from the input non translated virtual address. Since the lower bits never change there is no reason to place these lower bits on a longer critical path. The cache and lsu were previously using the lower bits from the virtual address rather than the physical address. This change will allow us to keep the shorter critical path and reduce the complexity of the lsu, ifu, and cache drawings. Ross Thompson 2022-01-06 23:19:09 -0600
• 1d8451c2cf Capitalized LSU and IFU, changed MulDiv to MDU David Harris 2022-01-07 04:30:00 +0000
• 0e023e29d8 Code cleanup David Harris 2022-01-07 04:07:04 +0000
• c9c3bddc6d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-06 17:19:20 -0600
• 008ac20a43 Minor optimization to cache replacement. Ross Thompson 2022-01-06 17:19:14 -0600
• 08231d4e66 Tests cleanup: David Harris 2022-01-06 23:07:22 +0000
• cb68548b88 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-06 23:04:33 +0000
• fc4db84bbc Makefile make allclean David Harris 2022-01-06 23:04:30 +0000
• e5f9fbb238 Fixed multiplier nan boxing bug David Harris 2022-01-06 23:03:29 +0000
• b3ebce0365 some FPU test fixes Katherine Parry 2022-01-06 23:03:20 +0000
• e1db967417 Clean up of cachefsm. Ross Thompson 2022-01-06 16:32:49 -0600
• 1c96b22b8f More FP unpacking fix David Harris 2022-01-06 22:22:22 +0000
• 340752616d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-06 21:45:20 +0000
• 2b8e8707a7 Floating point test cleanup David Harris 2022-01-06 21:45:16 +0000
• 4a93c0e512 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-06 15:18:27 -0600
• 6bd447d570 Patched the ILA's debug2.xdc constraint file to work with the wally memory design. Ross Thompson 2022-01-06 15:18:18 -0600
• 2b4c81fe98 Fixed unpacking bug; regression runs again David Harris 2022-01-06 18:22:30 +0000
• 55e757db03 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-06 18:10:32 +0000
• c9aa21d5a3 FPU debug and configurable logic cleanup David Harris 2022-01-06 18:10:25 +0000
• 8c71daff11 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-06 11:56:23 -0600
• 42623141cd Updated fpga ILA constraints to match the new changes to the rtl. Ross Thompson 2022-01-06 11:56:09 -0600
• 7f66177769 Fixed bug in synthesis script. Ross Thompson 2022-01-05 23:07:36 -0600
• d30ad136f3 cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv. Ross Thompson 2022-01-05 22:56:18 -0600
• 365b2715ed More name cleanup in cache. Ross Thompson 2022-01-05 22:37:53 -0600