Kip Macsai-Goren
|
badc684f07
|
added copies of 64 bit tests to 32 bit periph and priv tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
282d06b45f
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Ross Thompson
|
9806babe9e
|
Renamed SelBusBuffer to SelFetchBuffer.
|
2022-12-05 17:51:13 -06:00 |
|
Ross Thompson
|
0fdbfb87eb
|
Removed commented code.
|
2022-12-05 17:21:56 -06:00 |
|
Ross Thompson
|
85366a287b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-05 17:20:12 -06:00 |
|
Ross Thompson
|
bcb927d172
|
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
|
2022-12-05 17:19:51 -06:00 |
|
rachanaerra
|
4f042b0adb
|
updated constraints file
|
2022-12-05 15:05:21 -06:00 |
|
Ross Thompson
|
2bcaacb179
|
Cache signal renames.
|
2022-12-04 16:09:09 -06:00 |
|
Ross Thompson
|
b84b709182
|
Optimized way selection logic.
|
2022-12-04 12:30:56 -06:00 |
|
Ross Thompson
|
74d5ccc2b1
|
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
|
2022-12-04 01:20:51 -06:00 |
|
Ross Thompson
|
62e495c739
|
Moved selectedway mux into cacheway. It makes way more sense there.
|
2022-12-04 01:15:47 -06:00 |
|
Ross Thompson
|
e1ac736d43
|
Rename LineByteMux to FetchbufferbyteSel.
|
2022-12-04 01:00:04 -06:00 |
|
Ross Thompson
|
128b3d20e7
|
Updated riscv arch test removed misaligned1.
|
2022-12-04 00:18:10 +00:00 |
|
Ross Thompson
|
de99663b97
|
Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit 70b89e5214.
|
2022-12-04 00:01:58 +00:00 |
|
Ross Thompson
|
b7d004b261
|
Removed old flow directory.
|
2022-12-03 10:28:39 -06:00 |
|
Ross Thompson
|
ec8ae6e3a8
|
removed imperas-riscv-tests-deleteme
|
2022-12-03 00:18:42 +00:00 |
|
Ross Thompson
|
d969ae35e5
|
removed unusedsrc directory as it was large 384MB!
|
2022-12-02 17:37:06 -06:00 |
|
Ross Thompson
|
9d960dec65
|
Removed design ware mult.
|
2022-12-02 16:51:12 -06:00 |
|
cturek
|
70b89e5214
|
Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
|
2022-12-02 21:44:29 +00:00 |
|
cturek
|
1f32603c30
|
Added flops to preproc
|
2022-12-02 20:31:08 +00:00 |
|
David Harris
|
9395414df3
|
Renamed FPUStallD to FCvtIntStallD
|
2022-12-02 11:55:23 -08:00 |
|
David Harris
|
d64cd715f9
|
Renamed DivStartE to IFDivStartE
|
2022-12-02 11:30:49 -08:00 |
|
David Harris
|
9c1b7e53e4
|
FPU divider working with execute stage stall
|
2022-12-02 11:11:53 -08:00 |
|
David Harris
|
01028e7088
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-02 04:28:50 -08:00 |
|
David Harris
|
4c6003d9e2
|
update test list
|
2022-12-02 04:28:47 -08:00 |
|
Ross Thompson
|
33e4361de5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 22:36:07 -06:00 |
|
David Harris
|
8afc054e74
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 16:27:36 -08:00 |
|
David Harris
|
ed39099405
|
reorder tests
|
2022-12-01 16:27:33 -08:00 |
|
Ross Thompson
|
1d9b5badee
|
Properly flush cacheLRU.
|
2022-12-01 17:32:58 -06:00 |
|
David Harris
|
f64c0589fe
|
FPU test list
|
2022-12-01 10:18:36 -08:00 |
|
Ross Thompson
|
da92cdccd0
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 11:47:54 -06:00 |
|
Ross Thompson
|
cb310bfb1d
|
Removed unused port on cacheway.
|
2022-12-01 11:47:48 -06:00 |
|
David Harris
|
558f0b655e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 08:15:51 -08:00 |
|
David Harris
|
4e5f62a5c1
|
code cleanup
|
2022-12-01 08:15:48 -08:00 |
|
Ross Thompson
|
b0b16acaf5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 17:19:04 -06:00 |
|
David Harris
|
aa26a97b36
|
signal sufixes in integer division
|
2022-11-30 15:15:37 -08:00 |
|
Ross Thompson
|
f9ffcf377b
|
Reverted the IROM/DTIM address range modelsim assignment.
|
2022-11-30 17:13:33 -06:00 |
|
Ross Thompson
|
bfd238a4fc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 13:30:37 -06:00 |
|
Ross Thompson
|
813b2963fb
|
More optimization.
|
2022-11-30 11:26:48 -06:00 |
|
Ross Thompson
|
da7b13ba0a
|
Removed reset on dirty cache bits.
|
2022-11-30 11:04:37 -06:00 |
|
Ross Thompson
|
5e5cca6ae1
|
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
|
2022-11-30 11:01:25 -06:00 |
|
Ross Thompson
|
ac3e02692b
|
Preparing to merge dirty and tag srams.
|
2022-11-30 10:40:48 -06:00 |
|
Ross Thompson
|
8692ccbafb
|
Intermediate commit. Replaced flip flop dirty bit array with sram.
|
2022-11-30 00:08:31 -06:00 |
|
cturek
|
e28a6901a9
|
div tests in sim-wally
|
2022-11-30 02:32:04 +00:00 |
|
Ross Thompson
|
e3577781b0
|
Optimization of cacheway.
|
2022-11-29 18:30:47 -06:00 |
|
Ross Thompson
|
1e2180ef98
|
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
|
2022-11-29 17:19:31 -06:00 |
|
Ross Thompson
|
5e550fe5e6
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 14:57:38 -06:00 |
|
Ross Thompson
|
9e4166407b
|
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
|
2022-11-29 14:51:09 -06:00 |
|
Ross Thompson
|
179d321683
|
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
|
2022-11-29 14:09:48 -06:00 |
|
Kip Macsai-Goren
|
66fcb2bffe
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 10:43:44 -08:00 |
|