Ross Thompson
9ec624702d
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Katherine Parry
0c2b7a1132
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
bbracker
751e606fb7
trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug
2021-06-26 08:30:58 -04:00
bbracker
c93b6abed2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-26 08:29:37 -04:00
bbracker
17afd9e5e8
temporarily disable PMP checking for EBU accesses.
2021-06-26 07:19:51 -04:00
bbracker
74833dc68c
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
Ross Thompson
d80ebab941
AMO and LR/SC instructions now working correctly.
...
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Abe
12eff2bc5f
Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs
2021-06-25 16:42:03 -04:00
Abe
2ab29c74f2
Fixed Coremark Score output printing. Also made it so that the loop that sets the iteration count increments iterations by 1 instead by increasing it by a factor of 10 each time (which was overkill for the timing that's needed to exit the loop)
2021-06-25 16:27:23 -04:00
Ross Thompson
57a7074800
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341
Working through a combo loop.
2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
5b47da21ba
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
34dbad967d
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
192171826b
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
d7e518991e
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
ac597d78c8
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Katherine Parry
7e3483b283
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
2155a4e485
Revert "fixed forwarding"
...
This reverts commit 86e369df52
2021-06-24 17:39:37 -04:00
Ross Thompson
6bab454b17
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
c02141697d
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
aeeaf6d919
Progress.
2021-06-24 13:05:22 -05:00
bbracker
86e369df52
fixed forwarding
2021-06-24 11:20:21 -04:00
bbracker
2d9c91096b
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
53d545cdfe
regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
bbracker
cee468b21a
whoops meant to remove notifications from busybear, not buildroot
2021-06-24 01:54:46 -04:00
bbracker
13df69abdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
be962cb1ff
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
286b4b5b26
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
8eed89616c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
349f6a9471
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
a514554eeb
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
fc851ca795
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
303f8e2a7f
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
67cf2e1c90
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
353a27f12f
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
7e06a3c04d
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
2c41da0275
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
3e19eba20d
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
bbracker
9b27cd6fb7
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
