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Configurable RISC-V Processor
1,087 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
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bbracker 53d545cdfe regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
riscv-coremark Commit message 2021-06-17 14:49:13 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined regression can overcome the fact that buildroots UART prints stuff 2021-06-24 02:00:01 -04:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore added slack notifier for long sims 2021-06-22 08:31:41 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor