19 Commits

Author	SHA1	Message	Date
Ross Thompson	7d749b201b	added support to due partial fpga simulation.	2021-09-26 15:00:00 -05:00
Ross Thompson	a7be88a43b	Changes to make fpga synthesizable. ... Added preload to test simple program on wally in fpga.	2021-09-22 10:54:13 -05:00
David Harris	67e191c6f3	Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries	2021-07-04 11:39:59 -04:00
Kip Macsai-Goren	d7e518991e	Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.	2021-06-24 20:01:11 -04:00
David Harris	802238643a	Removed two cycles of latency from the DTIM	2021-06-10 10:30:24 -04:00
David Harris	01d6ca1e2a	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
Ross Thompson	4322694f7a	Switch to use RV64IC for the benchmarks. ... Still not working correctly with the icache. instr addr correct got	2021-04-07 19:12:43 -05:00
bbracker	a3788eb218	added 1 tick delay to dtim flops	2021-03-25 02:23:30 -04:00
bbracker	85363e941d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	345254b5a3	slightly smarter dtim HREADY	2021-03-13 06:55:34 -05:00
David Harris	42275e92ed	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
bbracker	0f4a231543	first merge of ahb fix	2021-03-05 14:24:22 -05:00
Noah Boorstin	dfae278ffb	busybear: make imperas tests work again	2021-03-04 22:44:49 +00:00
Noah Boorstin	4833b36535	busybear: more adapting to new memory system	2021-03-01 18:50:42 +00:00
Noah Boorstin	6e70ae8b3d	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	aee44bb343	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00