Ross Thompson
d6c19e73f4
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
5b47da21ba
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
34dbad967d
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
192171826b
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
d7e518991e
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
ac597d78c8
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Katherine Parry
7e3483b283
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
2155a4e485
Revert "fixed forwarding"
...
This reverts commit 86e369df52
2021-06-24 17:39:37 -04:00
Ross Thompson
6bab454b17
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
c02141697d
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
aeeaf6d919
Progress.
2021-06-24 13:05:22 -05:00
bbracker
86e369df52
fixed forwarding
2021-06-24 11:20:21 -04:00
bbracker
2d9c91096b
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
53d545cdfe
regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
bbracker
cee468b21a
whoops meant to remove notifications from busybear, not buildroot
2021-06-24 01:54:46 -04:00
bbracker
13df69abdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
be962cb1ff
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
286b4b5b26
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
8eed89616c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
349f6a9471
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
a514554eeb
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
fc851ca795
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
303f8e2a7f
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
67cf2e1c90
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
353a27f12f
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
Kip Macsai-Goren
7e06a3c04d
Fixed mask assignment error, made usage, variables more clear
2021-06-22 13:31:06 -04:00
Kip Macsai-Goren
2c41da0275
Continued fixing fsm to work right with svmode
2021-06-22 13:29:49 -04:00
Kip Macsai-Goren
3e19eba20d
updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
2021-06-22 11:21:11 -04:00
bbracker
9b27cd6fb7
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
Ross Thompson
f79e5eaa47
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
3cbe4c9bc2
Improved some names in icache.
2021-06-21 16:40:37 -05:00
Kip Macsai-Goren
c0d52b905d
updated mmu test pagetables so that make can be run.
2021-06-21 12:26:47 -04:00
David Harris
7930c2ebb4
Commented out 100k tests to improve speed
2021-06-21 01:43:18 -04:00
David Harris
5d6dc82db2
Added Physical Address and Size to PMA Checker/MMU
2021-06-21 01:27:02 -04:00
David Harris
1ec90a5e1f
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
d2ec04564b
Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
2021-06-20 22:59:04 -04:00
bbracker
23f479d225
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
bbracker
bf3c2dc089
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-20 22:29:40 -04:00
bbracker
3000c27acd
linux actually uses FPU now!
2021-06-20 22:29:21 -04:00
Katherine Parry
2b67f25683
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-20 20:24:09 -04:00
bbracker
2643130c41
read from MSTATUS workaround because QEMU has incorrect MSTATUS
2021-06-20 10:11:39 -04:00
bbracker
14ae87ff0a
testbench update b/c QEMU extends 32b CSRs to 64b
2021-06-20 09:24:19 -04:00
bbracker
83a0a37f8e
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
