James E. Stine
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37fe5e56a8
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Sanitization some more on mult_cs.sv
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2021-10-18 05:24:16 -05:00 |
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James E. Stine
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d0ab43e4e8
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Update some on mult_cs and delete DW02_mult.v
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2021-10-18 05:06:49 -05:00 |
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James E. Stine
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de7b673e34
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Add hacky hand-made carry/save multiplier - will improve
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2021-10-16 10:37:29 -05:00 |
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Katherine Parry
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c34633804a
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cvtfp module documented
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2021-10-14 15:25:31 -07:00 |
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James E. Stine
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c5b99300e7
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Clean up some signals - beautification onging
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2021-10-14 17:12:00 -05:00 |
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Kip Macsai-Goren
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869c35ba1c
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Fixed typo in imperas64mmu tests causing PMP tests not to run.
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2021-10-14 13:42:24 -07:00 |
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Skylar Litz
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71397d5db9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-13 15:38:32 -07:00 |
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Skylar Litz
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4ca4e13ba2
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add StallM signal back to DivStartE control
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2021-10-13 15:34:40 -07:00 |
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James E. Stine
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1dba57dce7
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Update to fpdivsqrt to go on posedge as it should. Also an update to
individual regression test for TestFloat (still needs some tweaking)
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2021-10-13 17:14:42 -05:00 |
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bbracker
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4abc6fc915
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change infrastructure to expect only 6.3 million from buildroot
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2021-10-12 10:41:15 -07:00 |
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Shreya Sanghai
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4424006624
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added DESIGN_COMPLIER to forgotten config files
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2021-10-12 10:14:04 -07:00 |
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Katherine Parry
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b79021a73e
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lint warnings fixed
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2021-10-12 09:45:02 -07:00 |
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Katherine Parry
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539d21645f
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some fpu lint warnings fixed - still working on it
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2021-10-11 18:32:03 -07:00 |
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Shreya Sanghai
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0acf9fd746
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made redunantmul generate DW02_multp for synopsys sythnesis
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2021-10-11 11:54:39 -07:00 |
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Shreya Sanghai
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84ff2b49c7
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actually added redundant mul
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2021-10-11 11:29:13 -07:00 |
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David Harris
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af7903e1b2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-11 11:21:39 -07:00 |
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David Harris
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1cdc5db75d
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Extended lint to check rv32/64g (including fpu. Not clean yet.
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2021-10-11 11:20:42 -07:00 |
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Shreya Sanghai
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a1c9ffdf2b
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added redundant multiplier
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2021-10-11 11:20:12 -07:00 |
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David Harris
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ab6a796690
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Starting to optimize multiplier
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2021-10-11 11:06:07 -07:00 |
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David Harris
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f1190b6ceb
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intdiv cleanup
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2021-10-11 08:14:21 -07:00 |
|
David Harris
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4139f27d10
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Divider FSM simplification
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2021-10-10 22:24:14 -07:00 |
|
David Harris
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75c17dc372
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Major reorganization of regression and simulation and testbenches
|
2021-10-10 15:07:51 -07:00 |
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James E. Stine
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2b66615812
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Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
|
2021-10-10 15:44:01 -05:00 |
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bbracker
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13352eccda
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-10 13:12:44 -07:00 |
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bbracker
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161767cddd
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make regression expect what buildroot is actually able to reach
|
2021-10-10 13:12:36 -07:00 |
|
David Harris
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a6c6b2b974
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-10 12:26:15 -07:00 |
|
David Harris
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caf3c2de9b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-10 12:25:11 -07:00 |
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bbracker
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90ccd60790
|
simplify flopenrc's that didn't actually need to be flopenrc's
|
2021-10-10 12:25:05 -07:00 |
|
David Harris
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43d92f2507
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Divider cleanup
|
2021-10-10 12:24:44 -07:00 |
|
David Harris
|
6704e37597
|
Simplifying divider FSM
|
2021-10-10 12:21:43 -07:00 |
|
David Harris
|
4deae8019a
|
Simplifying divider FSM
|
2021-10-10 12:21:36 -07:00 |
|
David Harris
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2759f1fcb1
|
Moved & ~StallM from FSM into DivStartE
|
2021-10-10 11:49:32 -07:00 |
|
David Harris
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635fe181f8
|
Moved divide iteration register names to M stage
|
2021-10-10 11:30:53 -07:00 |
|
David Harris
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b713b6ca87
|
Simplified remainder for divide by 0
|
2021-10-10 11:20:07 -07:00 |
|
David Harris
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6988c8c37c
|
divider control signal simplificaiton
|
2021-10-10 10:55:02 -07:00 |
|
David Harris
|
c2bb0324c6
|
Removed negedge flops from divider
|
2021-10-10 10:41:13 -07:00 |
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bbracker
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2f02287f91
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-10 10:10:06 -07:00 |
|
bbracker
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a88ae5aaff
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use correct string formatting function
|
2021-10-10 10:09:59 -07:00 |
|
David Harris
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3aa9e088c8
|
Simplified divider sign handling
|
2021-10-10 08:35:26 -07:00 |
|
David Harris
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39bbeefa78
|
renamed DivStart
|
2021-10-10 08:32:04 -07:00 |
|
David Harris
|
64ed267825
|
renamed DivSigned
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2021-10-10 08:30:19 -07:00 |
|
Katherine Parry
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77fe00947e
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FMA matches diagram and lint warnings fixed
|
2021-10-09 17:38:10 -07:00 |
|
bbracker
|
6fce53d146
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make testbench-linux halt on some discrepancies with QEMUw
|
2021-10-09 17:22:30 -07:00 |
|
kipmacsaigoren
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96565f9435
|
rename adder in fpu for synthesis
|
2021-10-08 17:47:54 -05:00 |
|
kipmacsaigoren
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7fde7aae6e
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Merging new changes into the old one's I've made in the OKstate servers
|
2021-10-08 17:47:11 -05:00 |
|
Kip Macsai-Goren
|
303beaa083
|
updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully.
|
2021-10-08 15:40:18 -07:00 |
|
Kip Macsai-Goren
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f3058f94c6
|
removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.
|
2021-10-08 15:33:18 -07:00 |
|
kipmacsaigoren
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2d4623b49c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-10-08 12:01:44 -05:00 |
|
David Harris
|
3d0383c154
|
moved fp vectors into vectors subdirectory
|
2021-10-07 23:28:06 -04:00 |
|
David Harris
|
6dd85b80a2
|
Included TestFloat and SoftFloat
|
2021-10-07 23:03:45 -04:00 |
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