Jarred Allen
41f682f848
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Jarred Allen
106718b196
Remove rd2, working for non-compressed
2021-03-04 16:46:43 -05:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
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Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
Ross Thompson
52d95d415f
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Thomas Fleming
de3f2547f4
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
015b632eb1
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
b16846bddb
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Ross Thompson
9b3637bd87
RAS needs to be reset or preloaded. For now I just reset it.
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Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87
Added FlushF to hazard unit.
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Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
c6ebe7733b
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
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About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
5df7e959f3
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
Ross Thompson
78db3654c6
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
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This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
David Harris
37dba8fd26
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
Ross Thompson
3ec1f668fc
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Ross Thompson
30df1cdd25
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
David Harris
2357f5513b
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
d56d7a75a6
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
9d7e242596
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
