mmasserfrye
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6fad0dc8ed
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-11 16:16:23 +00:00 |
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mmasserfrye
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68da2f5fa1
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modified ppa.sv to match module name and added madzscript
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2022-05-11 16:13:01 +00:00 |
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David Harris
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8166fd772e
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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137b411bea
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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490902a655
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Updated PPA experiment
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2022-05-10 23:09:42 +00:00 |
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David Harris
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bb24aebebd
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Initial PPA study
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2022-05-10 20:48:47 +00:00 |
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David Harris
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04fd22aeb0
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endian swapper
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2022-05-08 06:51:50 +00:00 |
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David Harris
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4f1b0fdc64
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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David Harris
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1a5bfcf078
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Fixed bug in delegated interrupts not being taken
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2022-05-08 04:50:27 +00:00 |
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David Harris
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a516f89f22
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WFI terminates when an interrupt is pending even if interrupts are globally disabled
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2022-05-08 04:30:46 +00:00 |
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David Harris
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412d4656ed
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Zero'd wfiM when ZICSR not supported to fix hang in E tests
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2022-05-05 15:32:13 +00:00 |
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David Harris
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7f42ff06d2
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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f436e93fc5
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SFENCE.VMA should be illegal in user mode
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2022-05-05 14:59:52 +00:00 |
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David Harris
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9b7aab122e
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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7249879a74
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clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals
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2022-05-04 23:01:23 +00:00 |
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Kip Macsai-Goren
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99423993a9
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added explicit clears to mstatus.mie
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2022-05-04 23:00:17 +00:00 |
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Kip Macsai-Goren
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536df2b8ad
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Updated test libraries to reflect variable name changes
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2022-05-04 21:39:36 +00:00 |
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Kip Macsai-Goren
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35e619ae74
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renamed test_loop_setup to run_test_loop
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2022-05-04 21:39:09 +00:00 |
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Kip Macsai-Goren
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26dfe36c16
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renamed debug to extended signature
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2022-05-04 21:38:37 +00:00 |
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Kip Macsai-Goren
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b155effe66
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put privileged tests back into rv32/64gc
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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895a4f4832
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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a9a434fced
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removed fp-diabled test and leftover mimpid test
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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f36fdf940d
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removed instruction misaligned tests from trap tests, signatures
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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badbe0840f
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renamed all tests to have lower-case titles except for WALLY
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2022-05-04 21:20:25 +00:00 |
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David Harris
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8a43d6099b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-03 18:32:04 +00:00 |
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David Harris
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4b91fddc0a
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Illegal instruction fault when running FPU instruction with STATUS_FS = 0
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2022-05-03 18:32:01 +00:00 |
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David Harris
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3efbd2565a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-03 08:53:35 -07:00 |
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David Harris
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20bbe43a23
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clean up sram1p1rw; still doesn't work on Modelsim 2022.1
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2022-05-03 08:31:54 -07:00 |
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David Harris
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1166c40059
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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David Harris
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bcd8728b3e
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Switched to behavioral comparator for best PPA
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2022-05-03 11:00:39 +00:00 |
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David Harris
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b4a422f771
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Comparator experiments
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2022-05-03 10:54:30 +00:00 |
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David Harris
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057524b840
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Formatting cache.sv
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2022-05-03 10:53:20 +00:00 |
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David Harris
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9e50c3440d
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sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
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2022-05-03 03:50:41 -07:00 |
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David Harris
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0df73d203b
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Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
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2022-05-03 03:45:41 -07:00 |
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David Harris
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9e47fca2b7
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Changed loop variable in CLINT because of error only seen on VLSI
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2022-05-03 10:10:28 +00:00 |
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Kip Macsai-Goren
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64ba550493
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general test cleanup of comments and old files
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2022-04-29 19:55:29 +00:00 |
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Kip Macsai-Goren
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36f5624255
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re-renamed status-mie-s to status-sie
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2022-04-29 19:55:13 +00:00 |
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Kip Macsai-Goren
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75e90f193e
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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407cdfbab7
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renamed registers in test library to RISC-V ABI name rater than x2, etc..
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2022-04-29 18:52:42 +00:00 |
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Kip Macsai-Goren
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c0b56bfd27
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renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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c47ec36bc7
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removed old unused tests from wally arch tests
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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2f17edb5f4
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added missing output for sret
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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746fcfde30
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set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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aedf0341af
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added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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Skylar Litz
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64a537c59b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-27 10:50:19 -07:00 |
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Skylar Litz
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f2b6842edb
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fix AttemptedInstructionCount from ground zero
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2022-04-27 10:45:40 -07:00 |
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David Harris
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55d25a1a89
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Ignore intermediate files in synthesis sweeps
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2022-04-27 13:12:04 +00:00 |
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David Harris
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515270a8cf
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Added torture.tv test vectors
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2022-04-27 13:08:36 +00:00 |
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David Harris
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cce0a421be
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Checked in torture.tv
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2022-04-27 13:06:24 +00:00 |
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