Ross Thompson
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d07c44bcf6
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Merge branch 'multimanager' into main
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2022-09-07 10:54:27 -05:00 |
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David Harris
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8438546d52
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Fixed regression for divsqrt radix2
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2022-09-07 06:12:23 -07:00 |
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Ross Thompson
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9d5a7281b8
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Modified ram_ahb to work with different latencies.
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2022-09-04 14:46:15 -05:00 |
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David Harris
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247ce70348
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Fixed lint errors in square root and improved waveforms in testfloat
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2022-09-01 15:49:13 -07:00 |
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Ross Thompson
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fcd1465de1
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Renamed AHBCachebusdp to abhcacheinterface.
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2022-08-31 14:12:19 -05:00 |
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Ross Thompson
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d06c64094b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-31 11:38:29 -05:00 |
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Ross Thompson
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5b8f888e21
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Maybe fixed it?
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2022-08-30 18:08:34 -05:00 |
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Ross Thompson
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ccb3e9e24e
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Updates to wave file.
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2022-08-30 17:34:36 -05:00 |
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Ross Thompson
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96793d15c0
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more progress.
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2022-08-30 17:32:32 -05:00 |
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Ross Thompson
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2d6a6c6e44
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Temporary commit.
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2022-08-30 15:40:42 -05:00 |
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Ross Thompson
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63a824cca1
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More progress.
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2022-08-30 15:27:19 -05:00 |
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Ross Thompson
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a532eb61ba
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Progress.
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2022-08-30 14:17:00 -05:00 |
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David Harris
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5956fbdd62
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Fixed checking termination in testfloat testbench
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2022-08-30 10:55:21 -07:00 |
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David Harris
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81ec1ac858
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Separated out radix 2 and radix 4 stages into different modules
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2022-08-29 04:26:14 -07:00 |
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David Harris
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b4cb9a678a
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renamed srt to fdivsqrt
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2022-08-29 04:04:05 -07:00 |
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David Harris
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35d0a951d2
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Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
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2022-08-27 20:31:09 -07:00 |
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David Harris
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3959902c5b
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Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
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2022-08-27 05:31:56 -07:00 |
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David Harris
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bd6f2444cd
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Fixed address decoder hanging buildroot
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2022-08-26 22:01:25 -07:00 |
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Ross Thompson
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4ad7ccc7f7
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Possible fixes for earily messup of rv32ic and rv64ic configs.
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2022-08-25 14:42:08 -05:00 |
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Ross Thompson
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5cc4f1f1cd
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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Ross Thompson
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1e1646da90
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Added generate around ebu.
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2022-08-25 09:24:13 -05:00 |
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Ross Thompson
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22e989ac7b
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No longer need wally-pipelined-fpga.do.
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2022-08-24 18:10:45 -05:00 |
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Ross Thompson
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c636387613
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Katherine Parry
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8eeca3319c
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radix-2 1 copy passes testfloat
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2022-08-06 22:54:05 +00:00 |
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David Harris
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6ee8036ae7
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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Ross Thompson
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acd920ae2f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-01 22:09:11 -05:00 |
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David Harris
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e3b970d3ff
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Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
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Ross Thompson
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01359dbc4b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-31 12:48:51 -05:00 |
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David Harris
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449c80b5f7
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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55ab81e37b
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More riscof makefile tuning
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2022-07-25 21:15:56 +00:00 |
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David Harris
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6b172723bd
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Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
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2022-07-25 20:50:38 +00:00 |
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Ross Thompson
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334008630f
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Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
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2022-07-24 01:20:29 -05:00 |
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Ross Thompson
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856ac24686
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Removed replay from the config files.
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2022-07-24 00:34:11 -05:00 |
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Ross Thompson
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e12e6c3acd
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Added more i-cache signals to wave file.
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2022-07-24 00:24:13 -05:00 |
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Ross Thompson
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70032bf8f4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
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Ross Thompson
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0f586c9ed3
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Possible improvement to cache which removes the cpu_busy states.
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2022-07-22 23:20:37 -05:00 |
|
Daniel Torres
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b726b05d61
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fixed wally rv32e tests, updated regression makefile to new testflow
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2022-07-22 17:09:46 -07:00 |
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Katherine Parry
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ee7932c804
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divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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Ross Thompson
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6c8ac7851e
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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Ross Thompson
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ffda64587c
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Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
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2022-07-18 23:37:18 -05:00 |
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Katherine Parry
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e599f82b29
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
|
Katherine Parry
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921debf930
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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e251022269
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
|
Katherine Parry
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b069cfbec2
|
fixed error in divsqrt
|
2022-07-14 18:16:00 +00:00 |
|
Katherine Parry
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e05b2a07d2
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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Katherine Parry
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2ada8a8bc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
|
Katherine Parry
|
b728e5054d
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variable interations implemented in radix-4 divider
|
2022-07-11 18:30:21 -07:00 |
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Katherine Parry
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cd53ae67d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
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