Ross Thompson
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cefbcd1b0c
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Partially sd card read on fpga.
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2021-09-30 11:23:09 -05:00 |
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Ross Thompson
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7ca801113e
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
|
Ross Thompson
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7d749b201b
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added support to due partial fpga simulation.
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2021-09-26 15:00:00 -05:00 |
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Ross Thompson
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4d1b02c068
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Merge branch 'main' into fpga
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2021-09-26 13:22:53 -05:00 |
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Ross Thompson
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3a9bc1e8c1
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Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies
the flash card to dram.
Fixed latch issue in the sd card reader.
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2021-09-26 13:22:23 -05:00 |
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Ross Thompson
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af53657eaf
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Merge branch 'sdc' into fpga
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2021-09-25 19:33:07 -05:00 |
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Ross Thompson
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a213ecbdb2
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GPIO marker to indicate the sdc to dram transfer complete.
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2021-09-25 19:29:15 -05:00 |
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Ross Thompson
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c917f14b6b
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Almost done writting driver for flash card reader.
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2021-09-25 19:05:07 -05:00 |
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Ross Thompson
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69674f272a
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We now have a rough sdc read routine.
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2021-09-25 17:51:38 -05:00 |
|
Ross Thompson
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10b46981ff
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Updated ignore file.
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2021-09-24 18:48:45 -05:00 |
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Ross Thompson
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23425c8d71
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Write of the SDC address register is correct. The command register is not yet working.
The root problem is the command register needs to be reset at the end of the SDC transaction.
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2021-09-24 18:48:11 -05:00 |
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Ross Thompson
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86524a5f64
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Now have software interacting with the initialization and settting the address register.
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2021-09-24 18:30:26 -05:00 |
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Ross Thompson
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44196af61a
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Have program which checks for sdc init and issues read, but read done is
not correctly being read back by the software. The error is in how the
sdc indicates busy.
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2021-09-24 15:53:38 -05:00 |
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Kip Macsai-Goren
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052b8b97fd
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updated pmp outputs with new exectuaion tests
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2021-09-24 16:30:16 -04:00 |
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Kip Macsai-Goren
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57fbd75ae3
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updated execute tests, light cleanup, privilege mode changes still need fix.
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2021-09-24 16:29:56 -04:00 |
|
Kip Macsai-Goren
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9784fc139c
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updated test library to include: simpler execution tests, widths for each read/write, outputs for pmpaddr writes.
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2021-09-24 16:28:53 -04:00 |
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Kip Macsai-Goren
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9ace858a19
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completed and cleaned up pmp tests, including execute tests
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2021-09-24 16:18:44 -04:00 |
|
Ross Thompson
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17c62b7d5a
|
Fixed lint errors in the SDC.
|
2021-09-24 12:38:48 -05:00 |
|
Ross Thompson
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4f7bc1be48
|
Added either the sdModel or constant driver for the SDC ports in all test benches.
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2021-09-24 12:31:51 -05:00 |
|
Ross Thompson
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80e37d2291
|
Added SDC defines to each config mode.
Added sd_top which is the sd card reader.
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2021-09-24 12:24:30 -05:00 |
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Ross Thompson
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9fdb1d3cc9
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setup so the sdc does not need to load a model in the imperas test bench.
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2021-09-24 11:30:52 -05:00 |
|
Ross Thompson
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c644e940c2
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Updated Imperas test bench to work with the SDC reader.
|
2021-09-24 11:22:54 -05:00 |
|
Ross Thompson
|
fea439b84d
|
SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
|
Ross Thompson
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92ea88c57b
|
Added clock gater and divider to generate the SDCCLK.
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2021-09-23 17:58:50 -05:00 |
|
Ross Thompson
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3cbbd15763
|
Partial implementation of SDC AHBLite interface.
|
2021-09-23 17:45:45 -05:00 |
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Ross Thompson
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3473f1e612
|
Started the AHBLite to SDC interface.
|
2021-09-22 18:08:38 -05:00 |
|
bbracker
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3f96ff0ac0
|
switch testbench-linux's interrupts from xcause to mip and improve warning messages
|
2021-09-22 12:33:11 -04:00 |
|
bbracker
|
8b97f8154f
|
update setup scripts to new testvector files
|
2021-09-22 12:31:10 -04:00 |
|
Ross Thompson
|
a7be88a43b
|
Changes to make fpga synthesizable.
Added preload to test simple program on wally in fpga.
|
2021-09-22 10:54:13 -05:00 |
|
Ross Thompson
|
ec0d2bc7d7
|
Initial SD Card reader.
|
2021-09-22 10:50:29 -05:00 |
|
Ross Thompson
|
221dbe92b2
|
Fixed the amo on dcache miss cpu stall issue.
|
2021-09-17 22:15:03 -05:00 |
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Ross Thompson
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e16c27225b
|
Finished adding the d cache flush. Required ensuring the write data, address, and size are
correct when transmitting to AHBLite interface.
|
2021-09-17 13:03:04 -05:00 |
|
Ross Thompson
|
cfd522da6b
|
The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.
|
2021-09-17 10:33:57 -05:00 |
|
Ross Thompson
|
0b1e59d075
|
Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
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2021-09-17 10:25:21 -05:00 |
|
Ross Thompson
|
615fd41e7b
|
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
|
2021-09-16 18:32:29 -05:00 |
|
Ross Thompson
|
348187ea70
|
Added counters to walk through d cache flush.
|
2021-09-16 17:12:51 -05:00 |
|
Ross Thompson
|
d901f60a6d
|
Added flush controls to cachway.
|
2021-09-16 16:56:48 -05:00 |
|
Ross Thompson
|
cae350abb7
|
Added invalidate to icache.
|
2021-09-16 16:15:54 -05:00 |
|
bbracker
|
a158558b83
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-09-15 17:31:11 -04:00 |
|
bbracker
|
ff5379fd95
|
fix regression
|
2021-09-15 17:30:59 -04:00 |
|
David Harris
|
9ae25b0cea
|
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
|
2021-09-15 13:14:00 -04:00 |
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bbracker
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ee1503a249
|
created script to determine which functions are most frequently used
|
2021-09-14 19:41:05 -04:00 |
|
bbracker
|
2738e9c900
|
IRQ timing template
|
2021-09-13 18:48:28 -04:00 |
|
David Harris
|
92385a1d51
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-09-13 12:41:07 -04:00 |
|
David Harris
|
9fa048980d
|
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
|
2021-09-13 12:40:40 -04:00 |
|
Ross Thompson
|
c60edb1a04
|
Merge branch 'main' into fpga
|
2021-09-13 09:45:59 -05:00 |
|
Ross Thompson
|
cd6d1e0b12
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-09-13 09:41:34 -05:00 |
|
David Harris
|
7be1160a48
|
Cleaned up wally-arch test scripts
|
2021-09-13 00:02:32 -04:00 |
|
David Harris
|
bbb6c7bef7
|
Restored old integer divider
|
2021-09-12 22:07:52 -04:00 |
|
Ross Thompson
|
296da4f437
|
FPGA test bench and test program.
|
2021-09-12 20:41:54 -05:00 |
|