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Configurable RISC-V Processor
1,709 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
3a9bc1e8c1
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Ross Thompson 3a9bc1e8c1 Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 
the flash card to dram.
Fixed latch issue in the sd card reader.
2021-09-26 13:22:23 -05:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 2021-09-26 13:22:23 -05:00
wally-pipelined Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 2021-09-26 13:22:23 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore Updated ignore file. 2021-09-24 18:48:45 -05:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor