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Configurable RISC-V Processor
1,686 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
9ace858a19
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Kip Macsai-Goren 9ace858a19 completed and cleaned up pmp tests, including execute tests
2021-09-24 16:18:44 -04:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
wally-pipelined switch testbench-linux's interrupts from xcause to mip and improve warning messages 2021-09-22 12:33:11 -04:00
.gitattributes
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor