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Author SHA1 Message Date
Ross Thompson
bf173b035c More cache simplifications. 2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595 Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
Ross Thompson
33beaa4593 Updates to linux wave. 2022-02-11 13:28:18 -06:00
Ross Thompson
d9f77d3659 Updated linux wave. 2022-02-11 13:15:42 -06:00
Ross Thompson
1a1629c62f linux wave cleanup. 2022-02-11 10:48:45 -06:00
Ross Thompson
febd019854 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02 Fixed subtle and infrequenct bug. 
Loading buildroot at 483M instructions started with a spill + ITLBMiss.  The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation.  However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation.  Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
 2022-02-11 10:46:06 -06:00
David Harris
de5e80696d Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
David Harris
cd243a965f merged synth.tcl 2022-02-11 00:21:24 +00:00
David Harris
4749941a22 Waive some synthesis warning messages 2022-02-11 00:20:23 +00:00
Ross Thompson
689c32215f Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
James Stine
39fd199538 Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
Ross Thompson
39be787821 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-10 17:52:27 -06:00
Ross Thompson
9fb612d4ff Updated wave files to reflect recent changes. 2022-02-10 17:52:19 -06:00
James Stine
a6db81e655 fix booboos from last push 2022-02-10 17:42:44 -06:00
James Stine
a9b1575499 Slight tweak to the great additions to the synthesis scripts. Pulls lib from addin directory by default for sky130. Also changed name from 90 and 130 to sky90 and sky130, respectively. 2022-02-10 17:30:00 -06:00
Ross Thompson
5fd22caed4 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
f716cce832 Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
104a9acf81 Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
fdb4f909fc Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
88c7a94aa9 Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
f12874ef80 Ignore saif files. 2022-02-09 19:30:26 -06:00
Ross Thompson
7ff715f44f More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
600c18845f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 19:14:39 -06:00
Ross Thompson
829c6ea264 Added explainations of synthesis variables in README. 2022-02-09 18:47:20 -06:00
Ross Thompson
8a10198d43 Added saif to synthDC flow. 2022-02-09 18:42:48 -06:00
Ross Thompson
4fd0154d03 Added commented out commands to generate saif file from vsim. 2022-02-09 18:40:45 -06:00
bbracker
fd4556393b rename dump-dts debug script 2022-02-10 00:10:09 +00:00
bbracker
7b52ff9fcf continue to rename devicetree to wally-virt 2022-02-10 00:08:28 +00:00
bbracker
3ebf6d7418 rename devicetree to wally-virt 2022-02-10 00:07:29 +00:00
Ross Thompson
02abb31f5a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 16:44:33 -06:00
Ross Thompson
ec9ac430cd Commented quit. 2022-02-09 16:44:26 -06:00
James E. Stine
186185ef8b Update on README.md for synthDC 2022-02-09 16:20:05 -06:00
Ross Thompson
74bccc468c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 16:11:31 -06:00
Ross Thompson
3bbc044d11 Added support for 90nm. 2022-02-09 16:06:27 -06:00
James E. Stine
2eef7ec0ee Add power analysis to synth.tcl 2022-02-09 16:04:20 -06:00
Ross Thompson
5a654a2874 Cleaned up synthesis flow. 2022-02-09 15:18:49 -06:00
Ross Thompson
380085ca20 Updated synthesis and Makefile to output into binned directories. 2022-02-09 15:06:42 -06:00
David Harris
793670d878 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-09 19:47:52 +00:00
David Harris
dbcad218dd Merged synthesiss scripts into main 2022-02-09 19:47:50 +00:00