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Added support for 90nm.

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This commit is contained in:
Ross Thompson 2022-02-09 16:06:27 -06:00
parent 5a654a2874
commit 3bbc044d11
3 changed files with 29 additions and 8 deletions
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17
synthDC/.synopsys_dc.setup
View File

@ -3,11 +3,18 @@
set CURRENT_DIR [exec pwd]
set search_path [list "./" ]
set tech $::env(TECH)
set timing_lib $::env(RISCV)/cad/lib
lappend search_path $timing_lib
set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
lappend search_path $s8lib
if {$tech == 130} {
set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib
lappend search_path $s8lib
} elseif {$tech == 90} {
set s9lib $timing_lib/sky90/tech_files
lappend search_path $s9lib
}
# Synthetic libraries
set synthetic_library [list dw_foundation.sldb]
@ -16,7 +23,11 @@ set synthetic_library [list dw_foundation.sldb]
set target_library [list]
#lappend target_library scc9gena_tt_1.2v_25C.db
lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
if {$tech == 130} {
lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
} elseif {$tech == 90} {
lappend target_library scc9gena_tt_1.2v_25C.db
}
# Set Link Library
set link_library "$target_library $synthetic_library"

3
synthDC/Makefile
View File

@ -9,10 +9,11 @@ VARIANT := 18T_ms
export DESIGN ?= wallypipelinedcore
export FREQ ?= 500
export CONFIG ?= rv32e
export TECH ?= 130
time := $(shell date +%F-%H-%M)
hash := $(shell git rev-parse --short HEAD)
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(FREQ)_MHz_$(time)_$(hash)
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash)
default:
@echo "Basic synthesis procedure for OSU/HMC/UNLV:"

17
synthDC/scripts/synth.tcl
View File

@ -81,7 +81,11 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
# Setting constraints on input ports
#set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
if {$tech == "130"} {
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
} elseif {$tech == "90"} {
set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
}
# Set input/output delay
set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
@ -89,7 +93,12 @@ set_output_delay 0.0 -max -clock $my_clk [all_outputs]
# Setting load constraint on output ports
#set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
if {$tech == "130"} {
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
} elseif {$tech == "90"} {
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
}
# Set the wire load model
set_wire_load_mode "top"
@ -216,7 +225,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
# redirect -append $filename { echo "\n\n\n//////////////// Critical paths through faddcvt ////////////////\n\n\n" }
# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
set filename [format "%s%s%s%s" $outputDir "reports/" $my_toplevel "_ifu_timing.rep"]
set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ifu_timing.rep"]
redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCF ////////////////\n\n\n" }
redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCNextF ////////////////\n\n\n" }
@ -316,4 +325,4 @@ set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"
redirect $filename { report_hierarchy }
#Quit
#quit # *** commented out so we can stay in the synopsis terminal after synthesis is done.
quit