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Added saif to synthDC flow.

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This commit is contained in:
Ross Thompson 2022-02-09 18:42:48 -06:00
parent fd4556393b
commit 8a10198d43
2 changed files with 15 additions and 14 deletions
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13
synthDC/Makefile
View File

@ -3,8 +3,6 @@
#
NAME := synth
# *** instead of variant can we select 130nm, 90nm, or 28nm?
VARIANT := 18T_ms
# defaults
export DESIGN ?= wallypipelinedcore
export FREQ ?= 500
@ -14,6 +12,7 @@ export TECH ?= 130
time := $(shell date +%F-%H-%M)
hash := $(shell git rev-parse --short HEAD)
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash)
export SAIFPOWER ?= 0
default:
@echo "Basic synthesis procedure for OSU/HMC/UNLV:"
@ -21,19 +20,16 @@ default:
@echo
synth:
# @sed -i 's/18T_ms/${VARIANT}/g' scripts/synth.tcl
# @sed -i 's/18T_ms/${VARIANT}/g' .synopsys_dc.setup
@echo "DC Synthesis"
@mkdir -p hdl/
@mkdir -p $(OUTPUTDIR)
@mkdir -p $(OUTPUTDIR)/reports
@mkdir -p $(OUTPUTDIR)/mapped
@mkdir -p $(OUTPUTDIR)/unmapped
ifeq ($(SAIFPOWER), 1)
cp -f ../pipelined/regression/power.saif .
endif
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
# @cp mapped/*.sdc ../../outputs/
# @cp mapped/*.vh ../../outputs/
# @sed -i 's/${VARIANT}/18T_ms/g' scripts/synth.tcl
# @sed -i 's/${VARIANT}/18T_ms/g' .synopsys_dc.setup
clean:
rm -rf alib-52 WORK analyzed $(NAME).out
@ -41,6 +37,7 @@ clean:
rm -f default.svf
rm -f command.log
rm -f filenames*.log
rm -f power.saif

16
synthDC/scripts/synth.tcl
View File

@ -3,8 +3,6 @@
# james.stine@okstate.edu 27 Sep 2015
#
# Enables name mapping
saif_map -start
# get outputDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR)
@ -12,6 +10,7 @@ set cfgName $::env(CONFIG)
# Config
set hdl_src "../pipelined/src"
set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
set saifpower $::env(SAIFPOWER)
eval file copy -force ${cfg} {hdl/}
eval file copy -force ${cfg} $outputDir
@ -19,6 +18,11 @@ eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Enables name mapping
if { $saifpower == 1 } {
saif_map -start
}
# Verilog files
set my_verilog_files [glob hdl/*]
@ -51,11 +55,11 @@ link
# Reset all constraints
reset_design
# SAIF power prediction (optional)
# set_power_prediction
# Power Dissipation Analysis
# read_saif -input vcd/mult.saif -instance_name stimulus/dut -auto_map_names -verbose
######### OPTIONAL !!!!!!!!!!!!!!!!
if { $saifpower == 1 } {
read_saif -input power.saif -instance_name testbench/dut/core -auto_map_names -verbose
}
# Set reset false path
set_false_path -from [get_ports reset]