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fix booboos from last push

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This commit is contained in:
James Stine 2022-02-10 17:42:44 -06:00
parent a9b1575499
commit a6db81e655
3 changed files with 6 additions and 15 deletions
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2
synthDC/.synopsys_dc.setup
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@ -27,7 +27,7 @@ set target_library [list]
#lappend target_library scc9gena_tt_1.2v_25C.db
if {$tech == "sky130"} {
lappend target_library ../addins/sky130_osu_sc_t12/12T_ms/lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
lappend target_library $s8lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
} elseif {$tech == "sky90"} {
lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
}

12
synthDC/README.md
View File

@ -5,7 +5,7 @@ This subdirectory contains synthesis scripts for use with Synopsys
scripts/synth.tcl.
Example Usage
make synth DESIGN=wallypipelinedcore FREQ=300
make synth DESIGN=wallypipelinedcore FREQ=500
environment variables
@ -13,7 +13,7 @@ DESIGN
Design provides the name of the output log. Default is synth.
FREQ
Frequency in Mhz. Default is 500
Frequency in MHz. Default is 500
CONFIG
The wally configuration file. Default is rv32e.
@ -24,8 +24,8 @@ CONFIG
TECH
The target standard cell library. Default is 130.
90: skywater 90nm tt 25C.
130: skywater 130nm tt 25C.
sky90: skywater 90nm TT 25C
sky130: skywater 130nm TT 25C
SAIFPOWER
Controls if power analysis is driven by switching factor or RTL modelsim simulation.
@ -34,7 +34,3 @@ SAIFPOWER
0: switching factor power analysis
1: RTL simulation driven power analysis.
Libraries in .synopsys_dc.setup file
set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib

7
synthDC/scripts/synth.tcl
View File

@ -3,18 +3,13 @@
# james.stine@okstate.edu 27 Sep 2015
#
if { [info exists ::env(SAIFPOWER)] } {
set saifpower $::env(SAIFPOWER)
} else {
set saifpower 0
}
# get outputDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR)
set cfgName $::env(CONFIG)
# Config
set hdl_src "../pipelined/src"
set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
set saifpower $::env(SAIFPOWER)
eval file copy -force ${cfg} {hdl/}
eval file copy -force ${cfg} $outputDir