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166 Commits

Author SHA1 Message Date
Jarred Allen
682050a33b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
Teo Ene
a3aa103dc7 Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
e43849b82c Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Domenico Ottolia
d67e28bf50 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Noah Boorstin
69e5319675 busybear: more progress 2021-03-23 14:49:30 -04:00
Noah Boorstin
24e403bc35 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
f3194c6388 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Noah Boorstin
d5bd5fa9d7 start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
15474f678d Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
849641f31e busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
2aa76b27e1 busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
3f897bbf53 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
74bcd9b994 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
5b1db9b6a2 Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
097e8edb3d Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
a2bf5ac202 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
09faa40eb6 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Teo Ene
57f1ca5259 Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0 adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e69376c823 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
4fd0ecff69 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
3e849f99a6 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
dfe6df2e00 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
041439c008 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
da758e9e14 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
3618a39087 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
9f8f0242ca Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Noah Boorstin
bfa7aedd35 busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Domenico Ottolia
d354cbd37d Add privileged testbench 2021-03-16 20:28:38 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
36452749d7 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
400791163e copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Ross Thompson
7ceef2b0c6 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
David Harris
56b690ccb9 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
318b642359 Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
a8b242a6ef busybear: account for CSR moving 2021-03-11 06:45:14 +00:00
Jarred Allen
4757794887 Return testbench to normal 2021-03-10 22:58:41 -05:00
Ross Thompson
845115302e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
f92f766573 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
dcae90e3ad I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00